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[Commit-gnuradio] r5754 - in gnuradio/branches/features/inband-usb/usrp/
|
From: |
gnychis |
|
Subject: |
[Commit-gnuradio] r5754 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib megacells toplevel/usrp_inband_usb |
|
Date: |
Fri, 8 Jun 2007 21:24:34 -0600 (MDT) |
Author: gnychis
Date: 2007-06-08 21:24:34 -0600 (Fri, 08 Jun 2007)
New Revision: 5754
Added:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_inst.v
Removed:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.bsf
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.cmp
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.inc
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512_bb.v
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/data_packet_fifo.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Merging -r5234:5752 from branches/developers/thottelt/inband
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -1,197 +1,205 @@
module chan_fifo_reader
- ( input reset,
- input tx_clock,
- input tx_strobe,
- input [31:0]adc_clock,
- input [3:0] samples_format,
- input [15:0] fifodata,
- input pkt_waiting,
- output reg rdreq,
- output reg skip,
- output reg [15:0]tx_q,
- output reg [15:0]tx_i,
- output reg overrun,
- output reg underrun) ;
+ ( reset, tx_clock, tx_strobe, adc_time, samples_format,
+ fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
+ underrun, tx_empty ) ;
+ parameter MAX_PAYLOAD = 504 ;
+
+ input wire reset ;
+ input wire tx_clock ;
+ input wire tx_strobe ;
+ input wire [31:0] adc_time ;
+ input wire [3:0] samples_format ;
+ input wire [31:0] fifodata ;
+ input wire pkt_waiting ;
+ output reg rdreq ;
+ output reg skip ;
+ output reg [15:0] tx_q ;
+ output reg [15:0] tx_i ;
+ output reg underrun ;
+ output reg tx_empty ;
+
// Should not be needed if adc clock rate < tx clock rate
- `define JITTER 5
+ // Used only to debug
+ `define JITTER 5
//Samples format
// 16 bits interleaved complex samples
- `define QI16 4'b0
+ `define QI16 4'b0
// States
- `define IDLE 4'd0
- `define READ 4'd1
- `define HEADER1 4'd2
- `define HEADER2 4'd3
- `define TIMESTAMP1 4'd4
- `define TIMESTAMP2 4'd5
- `define WAIT 4'd6
- `define WAITSTROBE 4'd7
- `define SENDWAIT 4'd8
- `define SEND 4'd9
- `define FEED 4'd10
- `define DISCARD 4'd11
+ `define IDLE 4'd0
+ `define READ 4'd1
+ `define HEADER 4'd2
+ `define TIMESTAMP 4'd3
+ `define WAIT 4'd4
+ `define WAITSTROBE 4'd5
+ `define SEND 4'd6
+ `define DISCARD 4'd7
- // State registers
- reg[3:0] reader_state;
- reg[3:0] reader_next_state;
+ // Header format
+ `define PAYLOAD 8:0
+ `define ENDOFBURST 27
+ `define STARTDOFBURST 28
+
+
+ /* State registers */
+ reg [3:0] reader_state;
+
+ reg [8:0] payload_len;
+ reg [8:0] read_len;
+ reg [31:0] timestamp;
+ reg burst;
- //Variables
- reg[8:0] payload_len;
- reg[8:0] read_len;
- reg[31:0] timestamp;
- reg burst;
- reg qsample;
- always @(posedge tx_clock)
- begin
- if (reset)
+ always @(posedge tx_clock)
+ begin
+ if (reset)
begin
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- rdreq <= 0;
- skip <= 0;
- overrun <= 0;
- underrun <= 0;
- burst <= 0;
- qsample <= 1;
- end
+ reader_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ underrun <= 0;
+ burst <= 0;
+ tx_empty <= 1;
+ tx_q <= 0;
+ tx_i <= 0;
+ end
else
- begin
- reader_state = reader_next_state;
+ begin
case (reader_state)
`IDLE:
- begin
- if (pkt_waiting == 1)
- begin
- reader_next_state <= `READ;
- rdreq <= 1;
- underrun <= 0;
- end
- else if (burst == 1)
+ begin
+ if (pkt_waiting == 1)
+ begin
+ reader_state <= `READ;
+ rdreq <= 1;
+ underrun <= 0;
+ end
+ else if (burst == 1)
underrun <= 1;
- end
+
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
+ end
- // Just wait for the fifo data to arrive
+ /* Just wait for the fifodata to show up */
`READ:
- begin
- reader_next_state <= `HEADER1;
- end
+ begin
+ reader_state <= `HEADER;
+
+ if (tx_strobe)
+ tx_empty <= 1 ;
+ end
- // First part of the header
- `HEADER1:
- begin
- reader_next_state <= `HEADER2;
-
- //Check Start burst flag
- if (fifodata[3] == 1)
- burst <= 1;
+ /* Process header */
+ `HEADER:
+ begin
+ reader_state <= `TIMESTAMP;
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
+
+ //Check Start/End burst flag
+ if (fifodata[`STARTDOFBURST] == 1
+ && fifodata[`ENDOFBURST] == 1)
+ burst <= 0;
+ else if (fifodata[`STARTDOFBURST] == 1)
+ burst <= 1;
+ else if (fifodata[`ENDOFBURST] == 1)
+ burst <= 0;
+
+ payload_len <= fifodata[`PAYLOAD] ;
+ read_len <= 0;
- if (fifodata[4] == 1)
- burst <= 0;
- end
+ rdreq <= 0;
+ end
- // Read payload length
- `HEADER2:
- begin
- payload_len <= (fifodata & 16'h1FF);
- read_len <= 9'd0;
- reader_next_state <= `TIMESTAMP1;
- end
-
- `TIMESTAMP1:
- begin
- timestamp <= {fifodata, 16'b0};
- rdreq <= 0;
- reader_next_state <= `TIMESTAMP2;
- end
+ `TIMESTAMP:
+ begin
+ timestamp <= fifodata;
+ reader_state <= `WAIT;
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
+ end
- `TIMESTAMP2:
- begin
- timestamp <= timestamp + fifodata;
- reader_next_state <= `WAIT;
- end
-
- // Decide if we wait, send or discard samples
+ // Decide if we wait, send or discard samples
`WAIT:
- begin
+ begin
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
+
+ // Let's send it
+ if ((timestamp < adc_time + `JITTER
+ && timestamp > adc_time)
+ || timestamp == 32'hFFFFFFFF)
+ reader_state <= `WAITSTROBE;
// Wait a little bit more
- if (timestamp > adc_clock + `JITTER)
- reader_next_state <= `WAIT;
- // Let's send it
- else if ((timestamp < adc_clock + `JITTER
- && timestamp > adc_clock)
- || timestamp == 32'hFFFFFFFF)
- begin
- reader_next_state <= `WAITSTROBE;
- end
+ else if (timestamp > adc_time + `JITTER)
+ reader_state <= `WAIT;
// Outdated
- else if (timestamp < adc_clock)
- begin
- reader_next_state <= `DISCARD;
- skip <= 1;
+ else if (timestamp < adc_time)
+ begin
+ reader_state <= `DISCARD;
+ skip <= 1;
end
- end
+ end
- // Wait for the transmit chain to be ready
+ // Wait for the transmit chain to be ready
`WAITSTROBE:
- begin
- // If end of payload...
- if (read_len == payload_len)
+ begin
+ // If end of payload...
+ if (read_len == payload_len)
+ begin
+ reader_state <= `DISCARD;
+ skip <= (payload_len < MAX_PAYLOAD);
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
+ end
+ else if (tx_strobe == 1)
+ begin
+ reader_state <= `SEND;
+ rdreq <= 1;
+ end
+ end
+
+ // Send the samples to the tx_chain
+ `SEND:
+ begin
+ reader_state <= `WAITSTROBE;
+ read_len <= read_len + 9'd4;
+ tx_empty <= 0;
+ rdreq <= 0;
+
+ case(samples_format)
+ `QI16:
begin
- reader_next_state <= `DISCARD;
- skip <= (payload_len < 508);
+ tx_i <= fifodata[15:0];
+ tx_q <= fifodata[31:16];
end
-
- if (tx_strobe == 1)
- reader_next_state <= `SENDWAIT;
- end
-
- `SENDWAIT:
- begin
- rdreq <= 1;
- reader_next_state <= `SEND;
- end
-
- // Send the samples to the tx_chain
- `SEND:
- begin
- reader_next_state <= `WAITSTROBE;
- rdreq <= 0;
- read_len <= read_len + 2;
- case(samples_format)
- `QI16:
- begin
- tx_q <= qsample ? fifodata : 16'bZ;
- tx_i <= ~qsample ? fifodata : 16'bZ;
- qsample <= ~ qsample;
- end
+
+ // Assume 16 bits complex samples by default
default:
- begin
- // Assume 16 bits complex samples by default
- $display ("Error unknown samples format");
- tx_q <= qsample ? fifodata : 16'bZ;
- tx_i <= ~qsample ? fifodata : 16'bZ;
- qsample <= ~ qsample;
- end
- endcase
- end
+ begin
+ tx_i <= fifodata[15:0];
+ tx_q <= fifodata[31:16];
+ end
+ endcase
+ end
`DISCARD:
- begin
- skip <= 0;
- reader_next_state <= `IDLE;
- end
+ begin
+ skip <= 0;
+ reader_state <= `IDLE;
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
+ end
default:
- begin
- $display ("Error unknown state");
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- end
+ begin
+ $display ("Error unknown state");
+ reader_state <= `IDLE;
+ end
endcase
end
end
-endmodule
\ No newline at end of file
+endmodule
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v (from
rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,110 @@
+module channel_ram
+ ( // System
+ input txclk,
+ input reset,
+
+ // USB side
+ input [31:0] datain,
+ input WR,
+ input WR_done,
+ output have_space,
+
+ // Reader side
+ output [31:0] dataout,
+ input RD,
+ input RD_done,
+ output packet_waiting);
+
+ reg [6:0] wr_addr, rd_addr;
+ reg [1:0] which_ram_wr, which_ram_rd;
+ reg [2:0] nb_packets;
+
+ reg [31:0] ram0 [0:127];
+ reg [31:0] ram1 [0:127];
+ reg [31:0] ram2 [0:127];
+ reg [31:0] ram3 [0:127];
+
+ reg [31:0] dataout0;
+ reg [31:0] dataout1;
+ reg [31:0] dataout2;
+ reg [31:0] dataout3;
+
+ wire wr_done_int;
+ wire rd_done_int;
+
+ // USB side
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
+
+ assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
+
+ always @(posedge txclk)
+ if(reset)
+ wr_addr <= 0;
+ else if (WR_done)
+ wr_addr <= 0;
+ else if (WR)
+ wr_addr <= wr_addr + 7'd1;
+
+ always @(posedge txclk)
+ if(reset)
+ which_ram_wr <= 0;
+ else if (wr_done_int)
+ which_ram_wr <= which_ram_wr + 2'd1;
+
+ assign have_space = (nb_packets < 3);
+
+ // Reader side
+ always @(posedge txclk) dataout0 <= ram0[rd_addr];
+ always @(posedge txclk) dataout1 <= ram1[rd_addr];
+ always @(posedge txclk) dataout2 <= ram2[rd_addr];
+ always @(posedge txclk) dataout3 <= ram3[rd_addr];
+
+ assign dataout = (which_ram_rd[1]) ?
+ (which_ram_rd[0] ? dataout3 :
dataout2) :
+ (which_ram_rd[0] ? dataout1 :
dataout0);
+
+ reg next_packet;
+ assign rd_done_int = ((RD && (rd_addr == 7'd127)) || RD_done);
+
+ always @(posedge txclk)
+ if (reset)
+ rd_addr <= 0;
+ else if (RD_done)
+ rd_addr <= 0;
+ else if (RD) rd_addr <= rd_addr + 7'd1;
+
+ always @(posedge txclk)
+ if (reset)
+ begin
+ which_ram_rd <= 0;
+ next_packet <= 0;
+ end
+ else if (next_packet)
+ begin
+ which_ram_rd <= which_ram_rd + 2'd1;
+ next_packet <= 0;
+ end
+ else if (rd_done_int)
+ next_packet <= 1;
+
+ assign packet_waiting = (nb_packets > 0);
+
+ always @(posedge txclk)
+ if (reset)
+ nb_packets <= 0;
+ else if (wr_done_int & ~rd_done_int)
+ nb_packets <= nb_packets + 3'd1;
+ else if (rd_done_int & ~wr_done_int)
+ nb_packets <= nb_packets - 3'd1;
+
+endmodule
\ No newline at end of file
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/data_packet_fifo.v
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/data_packet_fifo.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -1,128 +1,118 @@
module data_packet_fifo
( input reset,
input clock,
- input [15:0]ram_data_in,
+ input [31:0]ram_data_in,
input write_enable,
output reg have_space,
- output reg [15:0]ram_data_out,
+ output reg [31:0]ram_data_out,
output reg pkt_waiting,
+ output reg isfull,
+ output reg [1:0]usb_ram_packet_out,
+ output reg [1:0]usb_ram_packet_in,
input read_enable,
input pkt_complete,
input skip_packet) ;
/* Some parameters for usage later on */
- parameter DATA_WIDTH = 16 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter PKT_DEPTH = 128 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
- reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+ reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
/* Create the address signals */
- reg [7:0] usb_ram_offset_out ;
- reg [1:0] usb_ram_packet_out ;
- reg [7:0] usb_ram_offset_in ;
- reg [1:0] usb_ram_packet_in ;
+ reg [6:0] usb_ram_offset_out ;
+ //reg [1:0] usb_ram_packet_out ;
+ reg [6:0] usb_ram_offset_in ;
+ //reg [1:0] usb_ram_packet_in ;
- wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
- wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
- reg isfull;
+ wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
+ wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
+ //reg isfull;
assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
// Check if there is one full packet to process
- always @(usb_ram_ain, usb_ram_aout)
+ always @(usb_ram_ain, usb_ram_aout, isfull)
begin
- if (reset)
- pkt_waiting <= 0;
- else if (usb_ram_ain >= usb_ram_aout)
- pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+ if (usb_ram_ain == usb_ram_aout)
+ pkt_waiting <= isfull ;
+ else if (usb_ram_ain > usb_ram_aout)
+ pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH;
else
- pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
256;
+ pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >=
PKT_DEPTH;
end
-
+
// Check if there is room
- always @(usb_ram_ain, usb_ram_aout)
+ always @(usb_ram_ain, usb_ram_aout, isfull)
begin
- if (reset)
- have_space <= 1;
- else if (usb_ram_ain == usb_ram_aout)
+ if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
- have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS -
1);
+ have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH *
(NUM_PACKETS - 1))? 1'b1 : 1'b0;
else
- have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
+ have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
- /* RAM Write Address process */
- always @(posedge clock)
- begin
- if( reset )
- begin
- usb_ram_offset_in <= 0 ;
- usb_ram_packet_in <= 0 ;
- end
- else
- if( pkt_complete )
- begin
- usb_ram_packet_in <= usb_ram_packet_in + 1;
- usb_ram_offset_in <= 0;
- end
- else if( write_enable )
- begin
- if (usb_ram_offset_in == 8'b11111111)
- begin
- usb_ram_offset_in <= 0;
- usb_ram_packet_in <= usb_ram_packet_in + 1;
- end
- else
- usb_ram_offset_in <= usb_ram_offset_in + 1 ;
- if (usb_ram_ain + 1 == usb_ram_aout)
- isfull <= 1;
- end
- end
- /* RAM Writing process */
+
+ /* RAM Writing/Reading process */
always @(posedge clock)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
+ ram_data_out <= usb_ram[usb_ram_aout] ;
end
- /* RAM Read Address process */
+ /* RAM Write/Read Address process */
always @(posedge clock)
begin
if( reset )
begin
usb_ram_packet_out <= 0 ;
usb_ram_offset_out <= 0 ;
+ usb_ram_offset_in <= 0 ;
+ usb_ram_packet_in <= 0 ;
isfull <= 0;
end
else
+ begin
if( skip_packet )
begin
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
usb_ram_offset_out <= 0 ;
+ isfull <= 0;
end
- else if(read_enable) begin
- if( usb_ram_offset_out == 8'b11111111 )
+ else if(read_enable)
+ begin
+ if( usb_ram_offset_out == 7'b1111111 )
begin
+ isfull <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
end
else
usb_ram_offset_out <= usb_ram_offset_out + 1 ;
- end
- if (usb_ram_ain == usb_ram_aout)
- isfull <= 0;
+ end
+ if( pkt_complete )
+ begin
+ usb_ram_packet_in <= usb_ram_packet_in + 1 ;
+ usb_ram_offset_in <= 0 ;
+ if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
+ isfull <= 1 ;
+ end
+ else if( write_enable )
+ begin
+ if (usb_ram_offset_in == 7'b1111111)
+ usb_ram_offset_in <= 7'b1111111 ;
+ else
+ usb_ram_offset_in <= usb_ram_offset_in + 1 ;
+ end
+ end
end
- /* RAM Reading Process */
- always @(posedge clock)
- begin
- ram_data_out <= usb_ram[usb_ram_aout] ;
- end
-
endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -1,183 +1,150 @@
module tx_buffer_inband
- ( input usbclk,
- input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
- input reset, // standard DSP-side reset
- input [15:0] usbdata,
- input wire WR,
- output wire have_space,
- output reg tx_underrun,
- input wire [3:0] channels,
- output [15:0] tx_i_0,
- output [15:0] tx_q_0,
- output [15:0] tx_i_1,
- output [15:0] tx_q_1,
- //NOT USED
- output reg [15:0] tx_i_2,
- output reg [15:0] tx_q_2,
- output reg [15:0] tx_i_3,
- output reg [15:0] tx_q_3,
- input txclk,
- input txstrobe,
- input clear_status,
- output wire tx_empty,
- output [11:0] debugbus
- );
+ ( usbclk, bus_reset, reset, usbdata, WR, have_space,
+ tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
+ tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe,
+ clear_status, tx_empty, debugbus
+ );
+
+ parameter NUM_CHAN = 2 ;
+ /* Debug paramters */
+ parameter STROBE_RATE_0 = 8'd1 ;
+ parameter STROBE_RATE_1 = 8'd2 ;
+
+ input wire usbclk ;
+ input wire bus_reset ; // Used here for the 257-Hack to
fix the FX2 bug
+ input wire reset ; // standard DSP-side reset
+ input wire [15:0] usbdata ;
+ input wire WR ;
+ input wire txclk ;
+ input wire txstrobe ;
+ /* Not used yet */
+ input wire [3:0] channels ;
+ input wire clear_status ;
+
+ output wire have_space ;
+ output wire tx_underrun ;
+ output wire tx_empty ;
+ output wire [15:0] tx_i_0 ;
+ output wire [15:0] tx_q_0 ;
+ output wire [15:0] tx_i_1 ;
+ output wire [15:0] tx_q_1 ;
+ output wire [15:0] debugbus ;
+ /* Not used yet */
+ output wire [15:0] tx_i_2 ;
+ output wire [15:0] tx_q_2 ;
+ output wire [15:0] tx_i_3 ;
+ output wire [15:0] tx_q_3 ;
+
- wire [15:0] tx_data_bus;
-
- wire WR_chan_0;
- wire chan_0_done;
- wire OR0;
- wire UR0;
+ /* To generate channel readers */
+ genvar i ;
+
+ /* These will eventually be external register */
+ reg [31:0] time_counter ;
+ wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
- wire WR_chan_1;
- wire chan_1_done;
- wire OR1;
- wire UR1;
+ /* Connections between tx_usb_fifo_reader and
+ cnannel/command processing blocks */
+ wire [31:0] tx_data_bus ;
+ wire [NUM_CHAN:0] chan_WR ;
+ wire [NUM_CHAN:0] chan_done ;
+
+ /* Connections between data block and the
+ FX2/TX chains */
+ wire [NUM_CHAN:0] chan_underrun ;
+ wire [NUM_CHAN:0] chan_txempty ;
- // NOT USED yet
- wire WR_cmd;
- wire cmd_done;
+ /* Conections between tx_data_packet_fifo and
+ its reader + strobe generator */
+ wire [31:0] chan_fifodata [NUM_CHAN:0] ;
+ wire chan_pkt_waiting [NUM_CHAN:0] ;
+ wire chan_rdreq [NUM_CHAN:0] ;
+ wire chan_skip [NUM_CHAN:0] ;
+ wire [NUM_CHAN:0] chan_have_space ;
+ wire chan_txstrobe [NUM_CHAN-1:0] ;
+
+ /* Outputs to transmit chains */
+ wire [15:0] tx_i [NUM_CHAN-1:0] ;
+ wire [15:0] tx_q [NUM_CHAN-1:0] ;
+
+ assign have_space = chan_have_space[0] & chan_have_space[1];
+
+ /* TODO: Figure out how to write this genericly */
+ assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
+ assign tx_underrun = chan_underrun[0] | chan_underrun[1] ;
+ assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
+ assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
+ assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
+ assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
+
+ /* Debug statement */
+ assign txstrobe_rate[0] = STROBE_RATE_0 ;
+ assign txstrobe_rate[1] = STROBE_RATE_1 ;
+ assign tx_q_2 = 16'b0 ;
+ assign tx_i_2 = 16'b0 ;
+ assign tx_q_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign debugbus = {7'b0, have_space, tx_empty, WR, chan_have_space[0],
+ chan_have_space[1], bus_reset, reset, chan_txempty[0],
+ chan_txempty[1]} ;
- //EXTERNAL REGISTER
- //TODO: increment it
- reg [31:0] time_counter;
- reg [7:0] txstrobe_rate_0;
- reg [7:0] txstrobe_rate_1;
-
-
- //Usb block
- wire [15:0] tupf_fifodata;
- wire tupf_pkt_waiting;
- wire tupf_rdreq;
- wire tupf_skip;
- wire tupf_have_space;
-
- usb_packet_fifo2 tx_usb_packet_fifo
- ( .reset (reset),
- .usb_clock (usbclk),
- .fpga_clock (txclk),
- .write_data (usbdata),
- .write_enable (WR),
- .read_data (tupf_fifodata),
- .pkt_waiting (tupf_pkt_waiting),
- .read_enable (tupf_rdreq),
- .skip_packet (tupf_skip),
- .have_space (tupf_have_space),
- .tx_empty (tx_empty)
- );
-
- usb_fifo_reader tx_usb_packet_reader (
- .reset(reset),
- .tx_clock(txclk),
- .tx_data_bus(tx_data_bus),
- .WR_chan_0(WR_chan_0),
- .WR_chan_1(WR_chan_1),
- .WR_cmd(WR_cmd),
- .chan_0_done(chan_0_done),
- .chan_1_done(chan_1_done),
- .cmd_done(cmd_done),
- .rdreq(tupf_rdreq),
- .skip(tupf_skip),
- .pkt_waiting(tupf_pkt_waiting),
- .fifodata(tupf_fifodata)
- );
+ usb_fifo_writer tx_usb_packet_writer
+ (
+ .bus_reset (bus_reset),
+ .usbclk (usbclk),
+ .WR_fx2 (WR),
+ .usbdata (usbdata),
+ .reset (reset),
+ .txclk (txclk),
+ .WR_channel (chan_WR),
+ .WR_done_channel (chan_done),
+ .ram_data (tx_data_bus)
+ );
-
- //Channel 0 block
- wire [15:0] tdpf_fifodata_0;
- wire tdpf_pkt_waiting_0;
- wire tdpf_rdreq_0;
- wire tdpf_skip_0;
- wire tdpf_have_space_0;
- wire txstrobe_chan_0;
-
- data_packet_fifo tx_data_packet_fifo_0
- ( .reset(reset),
- .clock(txclk),
- .ram_data_in(tx_data_bus),
- .write_enable(WR_chan_0),
- .ram_data_out(tdpf_fifodata_0),
- .pkt_waiting(tdpf_pkt_waiting_0),
- .read_enable(tdpf_rdreq_0),
- .pkt_complete(chan_0_done),
- .skip_packet(tdpf_skip_0),
- .have_space(tdpf_have_space_0)
- );
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_readers
+ channel_ram tx_data_packet_fifo
+ ( .reset (reset),
+ .txclk (txclk),
+ .datain (tx_data_bus),
+ .WR (chan_WR[i]),
+ .WR_done (chan_done[i]),
+ .have_space (chan_have_space[i]),
+ .dataout (chan_fifodata[i]),
+ .packet_waiting (chan_pkt_waiting[i]),
+ .RD (chan_rdreq[i]),
+ .RD_done (chan_skip[i])
+ );
- strobe_gen strobe_gen_0
- ( .clock(txclk),
- .reset(reset),
- .enable(1'b1),
- .rate(txstrobe_rate_0),
- .strobe_in(txstrobe),
- .strobe(txstrobe_chan_0)
- );
+ /*strobe_gen strobe_gen_chan
+ ( .clock (txclk),
+ .reset (reset),
+ .enable (1'b1),
+ .rate (txstrobe_rate[i]),
+ .strobe_in (txstrobe),
+ .strobe (chan_txstrobe[i])
+ );*/
- chan_fifo_reader tx_chan_0_reader (
- .reset(reset),
- .tx_clock(txclk),
- .tx_strobe(txstrobe),
- //.tx_strobe(txstrobe_chan_0),
- .adc_clock(time_counter),
- .samples_format(4'b0),
- .tx_q(tx_q_0),
- .tx_i(tx_i_0),
- .overrun(OR0),
- .underrun(UR0),
- .skip(tdpf_skip_0),
- .rdreq(tdpf_rdreq_0),
- .fifodata(tdpf_fifodata_0),
- .pkt_waiting(tdpf_pkt_waiting_0)
- );
+ chan_fifo_reader tx_chan_reader
+ ( .reset (reset),
+ .tx_clock (txclk),
+ .tx_strobe (txstrobe),
+ .adc_time (32'd0),
+ .samples_format (4'b0),
+ .tx_q (tx_q[i]),
+ .tx_i (tx_i[i]),
+ .underrun (chan_underrun[i]),
+ .skip (chan_skip[i]),
+ .rdreq (chan_rdreq[i]),
+ .fifodata (chan_fifodata[i]),
+ .pkt_waiting (chan_pkt_waiting[i]),
+ .tx_empty (chan_txempty[i])
+ );
+
+ end
+ endgenerate
-
- //Channel 1 block
- wire [15:0] tdpf_fifodata_1;
- wire tdpf_pkt_waiting_1;
- wire tdpf_rdreq_1;
- wire tdpf_skip_1;
- wire tdpf_have_space_1;
- wire txstrobe_chan_1;
-
- data_packet_fifo tx_data_packet_fifo_1
- ( .reset(reset),
- .clock(txclk),
- .ram_data_in(tx_data_bus),
- .write_enable(WR_chan_1),
- .ram_data_out(tdpf_fifodata_1),
- .pkt_waiting(tdpf_pkt_waiting_1),
- .read_enable(tdpf_rdreq_1),
- .pkt_complete(chan_1_done),
- .skip_packet(tdpf_skip_1),
- .have_space(tdpf_have_space_1)
- );
-
- strobe_gen strobe_gen_1
- ( .clock(txclk),
- .reset(reset),
- .enable(1'b1),
- .rate(txstrobe_rate_1),
- .strobe_in(txstrobe),
- .strobe(txstrobe_chan_1)
- );
-
- chan_fifo_reader tx_chan_1_reader (
- .reset(reset),
- .tx_clock(txclk),
- .tx_strobe(txstrobe),
- //.tx_strobe(txstrobe_chan_1),
- .adc_clock(time_counter),
- .samples_format(4'b0),
- .tx_q(tx_q_1),
- .tx_i(tx_i_1),
- .overrun(OR1),
- .underrun(UR1),
- .skip(tdpf_skip_1),
- .rdreq(tdpf_rdreq_1),
- .fifodata(tdpf_fifodata_1),
- .pkt_waiting(tdpf_pkt_waiting_1)
- );
-
endmodule // tx_buffer
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -1,19 +1,20 @@
module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset,
- rdreq, skip, done_chan, WR_chan, tx_data_bus);
+ rdreq, done_chan, WR_chan, tx_data_bus, have_space_chan);
/* Module parameters */
parameter NUM_CHAN = 2 ;
parameter WIDTH = 32 ;
+ parameter PKT_SIZE = 512 ;
input wire tx_clock ;
input wire reset ;
- input wire [WIDTH-1:0] fifodata ;
+ input wire [WIDTH-1:0] fifodata ;
input wire pkt_waiting ;
+ input wire [NUM_CHAN:0] have_space_chan ;
output reg rdreq ;
- output reg skip ;
output reg [NUM_CHAN:0] done_chan ;
output reg [NUM_CHAN:0] WR_chan ;
- output reg [WIDTH-1:0] tx_data_bus ;
+ output reg [WIDTH-1:0] tx_data_bus ;
@@ -31,100 +32,92 @@
/* Local registers */
reg [2:0] reader_state ;
- reg [2:0] reader_next_state ;
reg [4:0] channel ;
- reg [8:0] pkt_length ;
- reg [8:0] read_length ;
+ reg [9:0] pkt_length ;
+ reg [9:0] read_length ;
/* State Machine */
always @(posedge tx_clock)
begin
if (reset)
begin
- reader_state <= `IDLE ;
- reader_next_state <= `IDLE ;
+ reader_state <= `IDLE ;
rdreq <= 0 ;
- skip <= 0 ;
- WR_chan <= {NUM_CHAN+1{1'b0}} ;
- done_chan <= {NUM_CHAN+1{1'b0}} ;
+ WR_chan <= {(NUM_CHAN+1){1'b0}} ;
+ done_chan <= {(NUM_CHAN+1){1'b0}} ;
end
else
begin
- reader_state = reader_next_state ;
case(reader_state)
`IDLE:
begin
- reader_next_state <= pkt_waiting ? `WAIT :
`IDLE ;
+ reader_state <= pkt_waiting ? `WAIT : `IDLE
;
+ done_chan <= {(NUM_CHAN+1){1'b0}} ;
rdreq <= pkt_waiting ;
end
/* Wait for the fifo's data to show up */
`WAIT:
begin
- reader_next_state <= `READ_HEADER ;
+ reader_state <= `READ_HEADER ;
+ rdreq <= 0 ;
end
`READ_HEADER:
- begin
- reader_next_state <= `FORWARD_DATA ;
-
+ begin
/* Read header fields */
- channel <= (fifodata & 32'h1F0000) ;
- pkt_length <= (fifodata & 16'h1FF) + 4 ;
- read_length <= 9'd0 ;
+ channel <= (fifodata[20:16]) ;
+ pkt_length <= fifodata[8:0] + 10'd8 ;
+ read_length <= 10'd0 ;
- /* Forward data */
- case (channel)
- `TXCHAN0: WR_chan[0] <= 1 ;
- `TXCHAN1: WR_chan[1] <= 1 ;
- `TXCMD: WR_chan[2] <= 1 ;
- default: WR_chan <= 1 ;
- endcase
- tx_data_bus <= fifodata ;
+ if (have_space_chan[channel])
+ begin
+ reader_state <= `FORWARD_DATA ;
+ rdreq <= 1;
+ end
end
`FORWARD_DATA:
begin
- read_length <= read_length + 4 ;
+ read_length <= read_length + 10'd4 ;
// If end of payload...
if (read_length == pkt_length)
begin
- reader_next_state <= `SKIP_REST ;
- /* If the packet is 512 bytes, don't skip */
- skip <= pkt_length < 506 ;
+ reader_state <= rdreq ? `SKIP_REST : `IDLE ;
/* Data pushing done */
- WR_chan <= {NUM_CHAN+1{1'b0}} ;
+ WR_chan <= {(NUM_CHAN+1){1'b0}} ;
/* Notify next block */
- case (channel)
- `TXCHAN0: done_chan[0] <= 1 ;
- `TXCHAN1: done_chan[1] <= 1 ;
- `TXCMD: done_chan[2] <= 1 ;
- default: done_chan[0] <= 1 ;
- endcase
+ done_chan[channel] <= 1 ;
+
end
- else if (read_length == pkt_length - 4)
- rdreq <= 0 ;
+ else
+ WR_chan[channel] <= 1 ;
+ if (read_length == PKT_SIZE - 8)
+ rdreq <= 0;
+
/* Forward data */
tx_data_bus <= fifodata ;
end
`SKIP_REST:
begin
- reader_next_state <= pkt_waiting ? `READ_HEADER
: `IDLE ;
- done_chan <= {NUM_CHAN+1{1'b0}} ;
- rdreq <= pkt_waiting ;
- skip <= 0 ;
+ read_length <= read_length + 10'd4;
+ done_chan <= {(NUM_CHAN+1){1'b0}} ;
+
+ if (read_length == PKT_SIZE - 4)
+ reader_state <= `IDLE ;
+ else if (read_length == PKT_SIZE - 8)
+ rdreq <= 0 ;
end
default:
begin
reader_state <= `IDLE;
- reader_next_state <= `IDLE;
end
endcase
end
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
(from rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v)
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
(rev 0)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,181 @@
+
+module usb_fifo_writer
+ #(parameter BUS_WIDTH = 16,
+ parameter NUM_CHAN = 2,
+ parameter FIFO_WIDTH = 32)
+ (//FX2 Side
+ input bus_reset,
+ input usbclk,
+ input WR_fx2,
+ input [15:0]usbdata,
+
+ // TX Side
+ input reset,
+ input txclk,
+ output reg [NUM_CHAN:0] WR_channel,
+ output reg [FIFO_WIDTH-1:0] ram_data,
+ output reg [NUM_CHAN:0] WR_done_channel );
+
+
+ reg [8:0] write_count;
+
+ /* Fix FX2 bug */
+ always @(posedge usbclk)
+ if(bus_reset) // Use bus reset because this is on usbclk
+ write_count <= #1 0;
+ else if(WR_fx2 & ~write_count[8])
+ write_count <= #1 write_count + 9'd1;
+ else
+ write_count <= #1 WR_fx2 ? write_count : 9'b0;
+
+ reg WR_fx2_fixed;
+ reg [15:0]usbdata_fixed;
+
+ always @(posedge usbclk)
+ begin
+ WR_fx2_fixed <= WR_fx2 & ~write_count[8];
+ usbdata_fixed <= usbdata;
+ end
+
+ /* Used to convert 16 bits bus_data to the 32 bits wide fifo */
+ reg word_complete ;
+ reg [BUS_WIDTH-1:0] usbdata_delayed ;
+ reg writing ;
+ wire [FIFO_WIDTH-1:0] usbdata_packed ;
+ wire WR_packed ;
+
+ always @(posedge usbclk)
+ begin
+ if (bus_reset)
+ begin
+ word_complete <= 0 ;
+ writing <= 0 ;
+ end
+ else if (WR_fx2_fixed)
+ begin
+ writing <= 1 ;
+ if (word_complete)
+ word_complete <= 0 ;
+ else
+ begin
+ usbdata_delayed <= usbdata_fixed ;
+ word_complete <= 1 ;
+ end
+ end
+ else
+ writing <= 0 ;
+ end
+
+ assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
+ assign WR_packed = word_complete & writing ;
+
+ /* Make sure data are sync with usbclk */
+ reg [31:0]usbdata_usbclk;
+ reg WR_usbclk;
+
+ always @(posedge usbclk)
+ begin
+ if (WR_packed)
+ usbdata_usbclk <= usbdata_packed;
+ WR_usbclk <= WR_packed;
+ end
+
+ /* Cross clock boundaries */
+ reg [FIFO_WIDTH-1:0] usbdata_tx ;
+ reg WR_tx;
+ reg WR_1;
+ reg WR_2;
+ reg [31:0] usbdata_final;
+ reg WR_final;
+
+ always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
+
+ always @(posedge txclk)
+ if (reset)
+ WR_1 <= 0;
+ else
+ WR_1 <= WR_usbclk;
+
+ always @(posedge txclk)
+ if (reset)
+ WR_2 <= 0;
+ else
+ WR_2 <= WR_1;
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ WR_tx <= 0;
+ else
+ WR_tx <= WR_1 & ~WR_2;
+ end
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ WR_final <= 0;
+ else
+ begin
+ WR_final <= WR_tx;
+ if (WR_tx)
+ usbdata_final <= usbdata_tx;
+ end
+ end
+
+ /* Parse header and forward to ram */
+ reg [3:0]reader_state;
+ reg [4:0]channel ;
+ reg [9:0]read_length ;
+
+ parameter IDLE = 4'd0;
+ parameter HEADER = 4'd1;
+ parameter WAIT = 4'd2;
+ parameter FORWARD = 4'd3;
+
+ `define CHANNEL 20:16
+ `define PKT_SIZE 512
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ begin
+ reader_state <= 0;
+ WR_channel <= 0;
+ WR_done_channel <= 0;
+ end
+ else
+ case (reader_state)
+ IDLE: begin
+ if (WR_final)
+ reader_state <= HEADER;
+ end
+
+ // Store channel and forware header
+ HEADER: begin
+ channel <= (usbdata_final[`CHANNEL]) ;
+ WR_channel[usbdata_final[`CHANNEL]] <= 1;
+ ram_data <= usbdata_final;
+ read_length <= 10'd4 ;
+
+ reader_state <= WAIT;
+ end
+
+ WAIT: begin
+ WR_channel[channel] <= 0;
+
+ if (read_length == `PKT_SIZE)
+ reader_state <= IDLE;
+ else if (WR_final)
+ reader_state <= FORWARD;
+ end
+
+ FORWARD: begin
+ WR_channel[channel] <= 1;
+ ram_data <= usbdata_final;
+ read_length <= read_length + 10'd4;
+
+ reader_state <= WAIT;
+ end
+ endcase
+ end
+endmodule
\ No newline at end of file
Deleted:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_packet_fifo2.v
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
(from rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,116 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 184)
+ (text "fifo_1k" (rect 62 1 105 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 168 25 180)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 104)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+ (line (pt 0 104)(pt 16 104)(line_width 1))
+ )
+ (port
+ (pt 0 120)
+ (input)
+ (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+ (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+ (line (pt 0 120)(pt 16 120)(line_width 1))
+ )
+ (port
+ (pt 0 160)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8)))
+ (line (pt 0 160)(pt 16 160)(line_width 1))
+ )
+ (port
+ (pt 160 40)
+ (output)
+ (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+ (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
+ (line (pt 160 40)(pt 144 40)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "wrusedw[7..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
+ (text "wrusedw[7..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 3))
+ )
+ (port
+ (pt 160 96)
+ (output)
+ (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (line (pt 160 96)(pt 144 96)(line_width 3))
+ )
+ (port
+ (pt 160 120)
+ (output)
+ (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+ (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size
8)))
+ (line (pt 160 120)(pt 144 120)(line_width 1))
+ )
+ (port
+ (pt 160 136)
+ (output)
+ (text "rdusedw[7..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
+ (text "rdusedw[7..0]" (rect 73 130 135 143)(font "Arial"
(font_size 8)))
+ (line (pt 160 136)(pt 144 136)(line_width 3))
+ )
+ (drawing
+ (text "32 bits x 256 words" (rect 63 156 144 168)(font "Arial"
))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 168)(line_width 1))
+ (line (pt 144 168)(pt 16 168)(line_width 1))
+ (line (pt 16 168)(pt 16 16)(line_width 1))
+ (line (pt 16 84)(pt 144 84)(line_width 1))
+ (line (pt 16 148)(pt 144 148)(line_width 1))
+ (line (pt 16 66)(pt 22 72)(line_width 1))
+ (line (pt 22 72)(pt 16 78)(line_width 1))
+ (line (pt 16 114)(pt 22 120)(line_width 1))
+ (line (pt 22 120)(pt 16 126)(line_width 1))
+ )
+)
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
(from rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo_1k
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ );
+end component;
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
(from rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+FUNCTION fifo_1k
+(
+ aclr,
+ data[31..0],
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq
+)
+
+RETURNS (
+ q[31..0],
+ rdempty,
+ rdusedw[7..0],
+ wrfull,
+ wrusedw[7..0]
+);
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
(from rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,180 @@
+// megafunction wizard: %LPM_FIFO+%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_1k.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_1k (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [31:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [31:0] q;
+ output rdempty;
+ output [7:0] rdusedw;
+ output wrfull;
+ output [7:0] wrusedw;
+
+ wire sub_wire0;
+ wire [7:0] sub_wire1;
+ wire sub_wire2;
+ wire [31:0] sub_wire3;
+ wire [7:0] sub_wire4;
+ wire rdempty = sub_wire0;
+ wire [7:0] wrusedw = sub_wire1[7:0];
+ wire wrfull = sub_wire2;
+ wire [31:0] q = sub_wire3[31:0];
+ wire [7:0] rdusedw = sub_wire4[7:0];
+
+ dcfifo dcfifo_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdempty (sub_wire0),
+ .wrusedw (sub_wire1),
+ .wrfull (sub_wire2),
+ .q (sub_wire3),
+ .rdusedw (sub_wire4)
+ // synopsys translate_off
+ ,
+ .wrempty (),
+ .rdfull ()
+ // synopsys translate_on
+ );
+ defparam
+ dcfifo_component.add_ram_output_register = "OFF",
+ dcfifo_component.clocks_are_synchronized = "FALSE",
+ dcfifo_component.intended_device_family = "Cyclone",
+ dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+ dcfifo_component.lpm_numwords = 256,
+ dcfifo_component.lpm_showahead = "OFF",
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = 32,
+ dcfifo_component.lpm_widthu = 8,
+ dcfifo_component.overflow_checking = "ON",
+ dcfifo_component.underflow_checking = "ON",
+ dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_wave*.jpg FALSE
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
(from rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,131 @@
+// megafunction wizard: %LPM_FIFO+%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_1k.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module fifo_1k (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [31:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [31:0] q;
+ output rdempty;
+ output [7:0] rdusedw;
+ output wrfull;
+ output [7:0] wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_wave*.jpg FALSE
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_inst.v (from
rev 5752,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_inst.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_inst.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_inst.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -0,0 +1,13 @@
+fifo_1k fifo_1k_inst (
+ .aclr ( aclr_sig ),
+ .data ( data_sig ),
+ .rdclk ( rdclk_sig ),
+ .rdreq ( rdreq_sig ),
+ .wrclk ( wrclk_sig ),
+ .wrreq ( wrreq_sig ),
+ .q ( q_sig ),
+ .rdempty ( rdempty_sig ),
+ .rdusedw ( rdusedw_sig ),
+ .wrfull ( wrfull_sig ),
+ .wrusedw ( wrusedw_sig )
+ );
Deleted: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.bsf
Deleted: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.cmp
Deleted: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.inc
Deleted: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512.v
Deleted: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_512_bb.v
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-06-09 03:24:34 UTC (rev 5754)
@@ -1,4 +1,4 @@
-// -*- verilog -*-
+ // -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-09 03:24:34 UTC (rev 5754)
@@ -372,11 +372,11 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_writer.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
@@ -412,4 +412,5 @@
set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
\ No newline at end of file
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-09 03:17:57 UTC (rev 5753)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-09 03:24:34 UTC (rev 5754)
@@ -326,7 +326,7 @@
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_0(tx_debugbus),.debug_1(tx_debugbus),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
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- [Commit-gnuradio] r5754 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib megacells toplevel/usrp_inband_usb,
gnychis <=