[Commit-gnuradio] r5737 - gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top

[jcorgan]

Author: jcorgan
Date: 2007-06-08 10:57:49 -0600 (Fri, 08 Jun 2007)
New Revision: 5737

Added:
   gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf
Modified:
   gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf
   gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.rbf
   gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.v
Log:
wip

Modified: 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf    
    2007-06-08 02:12:21 UTC (rev 5736)
+++ 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.qsf    
    2007-06-08 16:57:49 UTC (rev 5737)
@@ -390,4 +390,5 @@
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/serial_io.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/strobe_gen.v
+set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_sar.srf
\ No newline at end of file

Modified: 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.rbf
===================================================================
(Binary files differ)

Added: 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf    
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf    
    2007-06-08 16:57:49 UTC (rev 5737)
@@ -0,0 +1,67 @@
+{ "Warning" "WSGN_SEARCH_FILE" 
"../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design 
file *, which is not specified as a design file for the current project, but 
contains definitions for * design units and * entities in project" {  } {  } 0 
0 "Using design file %1!s!, which is not specified as a design file for the 
current project, but contains definitions for %2!d! design units and %3!d! 
entities in project" 1 1}
+{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "write_done 
serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at 
serial_io.v(48): object \"write_done\" assigned a value but never read" {  } { 
{ "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } }  } 0 10036 "Verilog 
HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 
1 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) 
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): 
truncated value with size 32 to match size of target (12)" {  } { { 
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } }  } 0 10230 "Verilog 
HDL assignment warning at %3!s!: truncated value with size %1!d! to match size 
of target (%2!d!)" 1 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) 
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): 
truncated value with size 32 to match size of target (12)" {  } { { 
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } }  } 0 10230 "Verilog 
HDL assignment warning at %3!s!: truncated value with size %1!d! to match size 
of target (%2!d!)" 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is 
connected to a signal of width 12. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is 
connected to a signal of width 12. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_3 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_3\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_3" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 133 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_3 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_3\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_3" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 132 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_2 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_2\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_2" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 130 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_2 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_2\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_2" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 129 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_2 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_2\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_2" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 128 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_1 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_1\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_1" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 126 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_1 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_1\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_1" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 125 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_1 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_1\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_1" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 124 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_0 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_0\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_0" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 122 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_0 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_0\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_0" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 121 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_0 16 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_0\" is 
connected to a signal of width 16. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_0" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 120 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_3 7 8 " 
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_3\" is 
connected to a signal of width 7. The formal width of the signal in the module 
is 8.  Extra bits will be driven by GND." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_3" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 98 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be driven by GND." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_2 7 8 " 
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_2\" is 
connected to a signal of width 7. The formal width of the signal in the module 
is 8.  Extra bits will be driven by GND." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_2" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 97 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be driven by GND." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_1 7 8 " 
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_1\" is 
connected to a signal of width 7. The formal width of the signal in the module 
is 8.  Extra bits will be driven by GND." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_1" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 96 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be driven by GND." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_0 7 8 " 
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_0\" is 
connected to a signal of width 7. The formal width of the signal in the module 
is 8.  Extra bits will be driven by GND." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_0" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 95 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be driven by GND." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_debugen 4 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_debugen\" is connected to a 
signal of width 4. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_debugen" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 93 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxbref 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_rxbref\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxbref" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 91 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txbref 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_txbref\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txbref" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 90 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxaref 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_rxaref\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxaref" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 89 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txaref 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_txaref\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txaref" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 88 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is 
connected to a signal of width 8. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "rate rx_strobe_gen 32 
8 " "Warning: Port \"rate\" on the entity instantiation of \"rx_strobe_gen\" is 
connected to a signal of width 32. The formal width of the signal in the module 
is 8.  Extra bits will be ignored." {  } { { "../lib/sar_rx.v" "rx_strobe_gen" 
{ Text "H:/gnuradio/sar/gr-sar-fe/src/fpga/lib/sar_rx.v" 60 0 0 } }  } 0 0 
"Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a 
signal of width %3!d!. The formal width of the signal in the module is %4!d!.  
Extra bits will be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage11\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage10\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage9\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage8 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage8\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage8" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 97 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage7 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage7\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage7" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 96 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage6 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage6\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage6" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 95 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage5 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage5\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage5" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 94 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage4 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage4\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage4" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 93 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage3 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage3\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage3" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 92 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage2\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage1\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 
cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity 
instantiation of \"cordic_stage0\" is connected to a signal of width 16. The 
formal width of the signal in the module is 15.  Extra bits will be ignored." { 
 } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } }  } 0 0 "Port \"%1!s!\" 
on the entity instantiation of \"%2!s!\" is connected to a signal of width 
%3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will 
be ignored." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mag 14 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_mag\" is connected to a signal 
of width 14. The formal width of the signal in the module is 32.  Extra bits 
will be left dangling without any fanout logic." {  } { { 
"../lib/sar_control.v" "sr_mag" { Text 
"H:/gnuradio/sar/gr-sar-fe/src/fpga/lib/sar_control.v" 56 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 8 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a 
signal of width 8. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../lib/sar_control.v" "sr_mode" { Text 
"H:/gnuradio/sar/gr-sar-fe/src/fpga/lib/sar_control.v" 54 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 " 
"Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is 
connected to a signal of width 11. The formal width of the signal in the module 
is 32.  Extra bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a 
signal of width 20. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a 
signal of width 4. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } }  } 0 0 "Port 
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of 
width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits 
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\] 
data_in GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]\" 
with stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\] data_in 
GND " "Warning: Reduced register 
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\" with 
stuck data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" 
"master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND " 
"Warning: Reduced register 
\"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck 
data_in port to stuck value GND" {  } { { 
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text 
"H:/gnuradio/sar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } }  } 0 0 "Reduced 
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}

Modified: 
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.v  
2007-06-08 02:12:21 UTC (rev 5736)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.v  
2007-06-08 16:57:49 UTC (rev 5737)
@@ -160,7 +160,7 @@
      ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
        .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
        
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-       .readback_0(),.readback_1(),.readback_2(capabilities),.readback_3(),
+       
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
        .readback_4(),.readback_5(),.readback_6(),.readback_7()
        );