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[Commit-gnuradio] r5715 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5715 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
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Date: |
Wed, 6 Jun 2007 16:30:09 -0600 (MDT) |
Author: thottelt
Date: 2007-06-06 16:30:08 -0600 (Wed, 06 Jun 2007)
New Revision: 5715
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
Log:
added fx2 bug work around
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-06 21:20:55 UTC (rev 5714)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-06 22:30:08 UTC (rev 5715)
@@ -101,6 +101,7 @@
burst <= 0;
payload_len <= fifodata[8:0] ;
+ //payload_len <= 9'd504 ;
read_len <= 0;
rdreq <= 0;
@@ -121,20 +122,23 @@
tx_empty <= 1 ;
// Let's send it
- if ((timestamp < adc_time + `JITTER
+ /*if ((timestamp < adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
reader_state <= `WAITSTROBE;
// Wait a little bit more
else if (timestamp > adc_time + `JITTER)
reader_state <= `WAIT;
-
+
+
// Outdated
else if (timestamp < adc_time)
begin
reader_state <= `DISCARD;
skip <= 1;
- end
+ end*/
+
+ reader_state <= `WAITSTROBE;
end
// Wait for the transmit chain to be ready
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-06 21:20:55 UTC (rev 5714)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-06 22:30:08 UTC (rev 5715)
@@ -35,6 +35,7 @@
output wire [15:0] tx_i_3 ;
output wire [15:0] tx_q_3 ;
+
/* To generate channel readers */
genvar i ;
@@ -100,36 +101,8 @@
.WR_done_channel (chan_done),
.ram_data (tx_data_bus)
);
-
+
-
- /*fifo_1k tx_usb_packet_fifo
- ( .aclr (reset),
- .wrclk (usbclk),
- .rdclk (txclk),
- .data (tupf_fifodata_in),
- .wrreq (tupf_write_enable),
- .q (tupf_fifodata_out),
- .rdreq (tupf_rdreq),
- .wrfull (),
- .wrusedw (tupf_wrusedw),
- .rdempty (),
- .rdusedw (tupf_rdusedw)
- );
-
- usb_fifo_reader #(NUM_CHAN) tx_usb_packet_reader
- (
- .reset (reset),
- .tx_clock (txclk),
- .tx_data_bus (tx_data_bus),
- .WR_chan (WR_chan),
- .done_chan (done_chan),
- .rdreq (tupf_rdreq),
- .pkt_waiting (tupf_pkt_waiting),
- .fifodata (tupf_fifodata_out),
- .have_space_chan (tdpf_have_space)
- );*/
-
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
channel_ram tx_data_packet_fifo
@@ -145,14 +118,14 @@
.RD_done (chan_skip[i])
);
- strobe_gen strobe_gen_chan
+ /*strobe_gen strobe_gen_chan
( .clock (txclk),
.reset (reset),
.enable (1'b1),
.rate (txstrobe_rate[i]),
.strobe_in (txstrobe),
.strobe (chan_txstrobe[i])
- );
+ );*/
chan_fifo_reader tx_chan_reader
( .reset (reset),
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-06 21:20:55 UTC (rev 5714)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-06 22:30:08 UTC (rev 5715)
@@ -25,25 +25,44 @@
wire [FIFO_WIDTH-1:0] usbdata_packed ;
wire WR ;
- //assign usbdata_packed = {usbdata_delayed, usbdata} ;
- assign usbdata_packed = {usbdata, usbdata_delayed} ;
- assign WR = ~word_complete & writing ;
-
- always @(posedge usbclk)
+ reg [8:0] write_count;
+
+ always @(posedge usbclk)
+ if(bus_reset) // Use bus reset because this is on usbclk
+ write_count <= #1 0;
+ else if(WR_fx2 & ~write_count[8])
+ write_count <= #1 write_count + 9'd1;
+ else
+ write_count <= #1 WR_fx2 ? write_count : 9'b0;
+
+ reg WR_fx2_fixed;
+ reg [15:0]usbdata_fixed;
+
+ always @(posedge usbclk)
+ begin
+ WR_fx2_fixed <= WR_fx2 & ~write_count[8];
+ usbdata_fixed <= usbdata;
+ end
+
+ //assign usbdata_packed = {usbdata_delayed, usbdata} ;
+ assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
+ assign WR = word_complete & writing ;
+
+ always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
- else if (WR_fx2)
+ else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
- usbdata_delayed <= usbdata ;
+ usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
@@ -62,33 +81,33 @@
reg [FIFO_WIDTH-1:0] usbdata_tx ;
reg WR_tx;
- reg fresh;
-
- always @(posedge txclk)
- begin
- if (reset)
- begin
- WR_tx <= 0;
- fresh <= 1;
- end
- else if (WR_usbclk & ~WR_tx & fresh)
- begin
- usbdata_tx <= usbdata_usbclk ;
- WR_tx <= 1 ;
- end
- else if (WR_usbclk & WR_tx)
- begin
- WR_tx <= 0;
- fresh <= 0;
- end
- else if (WR_tx)
- begin
- WR_tx <= 0;
- fresh <= 1;
- end
- else if (~WR_usbclk)
- fresh <= 1;
- end
+ reg fresh;
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ begin
+ WR_tx <= 0;
+ fresh <= 1;
+ end
+ else if (WR_usbclk & ~WR_tx & fresh)
+ begin
+ usbdata_tx <= usbdata_usbclk ;
+ WR_tx <= 1 ;
+ end
+ else if (WR_usbclk & WR_tx)
+ begin
+ WR_tx <= 0;
+ fresh <= 0;
+ end
+ else if (WR_tx)
+ begin
+ WR_tx <= 0;
+ fresh <= 1;
+ end
+ else if (~WR_usbclk)
+ fresh <= 1;
+ end
reg [3:0]reader_state;
reg [4:0]channel ;
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-06 21:20:55 UTC (rev 5714)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-06 22:30:08 UTC (rev 5715)
@@ -126,7 +126,10 @@
usbdata = {packet[2*i+1],packet[2*i]};
i = i + 1 ;
end
+ // Reproduce FX2 Bug
@(posedge usbclock)
+ WR = 1;
+ @(posedge usbclock)
WR = 0;
/*@(posedge usbclock)
WR = 0;*/
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-06
21:20:55 UTC (rev 5714)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-06
22:30:08 UTC (rev 5715)
@@ -249,7 +249,7 @@
Project_File_1 = ./chan_fifo_readers_test.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181087600 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181169257 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
19 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = ./usb_packet_fifo_test.v
@@ -271,7 +271,7 @@
Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180995228 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181083437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181158584 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
20 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
@@ -285,11 +285,11 @@
Project_File_19 = ./strobe_gen_test.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = ./usb_fifo_writer_test.v
-Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181081874 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181165989 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = ./fake_fx2.v
-Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181088101 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181165192 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181073478 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181161472 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_23 = ../inband/usrp/fpga/megacells/fifo_1k.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
@@ -321,6 +321,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_writer.v 0 0}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1}
{Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0} {Z:/wc/simulations/fake_fx2.v
0 0} {Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
{Z:/wc/simulations/usb_fifo_writer_test.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
2007-06-06 21:20:55 UTC (rev 5714)
+++ gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
2007-06-06 22:30:08 UTC (rev 5715)
@@ -37,7 +37,7 @@
usbdata = 0 ;
i = 0 ;
- #40 reset = 0 ;
+ #400 reset = 0 ;
bus_reset = 0;
send_packet(100, 16'd0, 32'hFFFFFFFF);
@@ -48,10 +48,10 @@
end
always
- #13 usbclk = ~usbclk ;
+ #64 usbclk = ~usbclk ;
always
- #3 txclk = ~txclk ;
+ #48 txclk = ~txclk ;
task send_packet;
@@ -62,15 +62,16 @@
repeat (256) begin
@(posedge usbclk)
WR_fx2 = 1;
- if (i == 0) usbdata = channel;
- else if (i == 1) usbdata = length;
- else if (i == 2) usbdata = timestamp[31:16];
- else if (i == 3) usbdata = timestamp[15:0];
+ if (i == 1) usbdata = channel;
+ else if (i == 0) usbdata = length;
+ else if (i == 3) usbdata = timestamp[31:16];
+ else if (i == 2) usbdata = timestamp[15:0];
else usbdata = i;//{16'hFFFF - i,i};
i = i + 1;
end
-
@(posedge usbclk)
+ WR_fx2 = 1;
+ @(posedge usbclk)
WR_fx2 = 0;
i = 0;
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- [Commit-gnuradio] r5715 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations,
thottelt <=