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[Commit-gnuradio] r5700 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5700 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations |
|
Date: |
Tue, 5 Jun 2007 19:09:14 -0600 (MDT) |
Author: thottelt
Date: 2007-06-05 19:09:14 -0600 (Tue, 05 Jun 2007)
New Revision: 5700
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
gnuradio/branches/developers/thottelt/simulations/channel_ram_test.v
gnuradio/branches/developers/thottelt/simulations/full_chip.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
Log:
matt refactoring
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-06 00:36:25 UTC (rev 5699)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -119,15 +119,16 @@
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
-
- // Wait a little bit more
- if (timestamp > adc_time + `JITTER)
- reader_state <= `WAIT;
+
// Let's send it
- else if ((timestamp < adc_time + `JITTER
+ if ((timestamp < adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
- reader_state <= `WAITSTROBE;
+ reader_state <= `WAITSTROBE;
+ // Wait a little bit more
+ else if (timestamp > adc_time + `JITTER)
+ reader_state <= `WAIT;
+
// Outdated
else if (timestamp < adc_time)
begin
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -0,0 +1,110 @@
+module channel_ram
+ ( // System
+ input txclk,
+ input reset,
+
+ // USB side
+ input [31:0] datain,
+ input WR,
+ input WR_done,
+ output have_space,
+
+ // Reader side
+ output [31:0] dataout,
+ input RD,
+ input RD_done,
+ output packet_waiting);
+
+ reg [6:0] wr_addr, rd_addr;
+ reg [1:0] which_ram_wr, which_ram_rd;
+ reg [2:0] nb_packets;
+
+ reg [31:0] ram0 [0:127];
+ reg [31:0] ram1 [0:127];
+ reg [31:0] ram2 [0:127];
+ reg [31:0] ram3 [0:127];
+
+ reg [31:0] dataout0;
+ reg [31:0] dataout1;
+ reg [31:0] dataout2;
+ reg [31:0] dataout3;
+
+ wire wr_done_int;
+ wire rd_done_int;
+
+ // USB side
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
+
+ assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
+
+ always @(posedge txclk)
+ if(reset)
+ wr_addr <= 0;
+ else if (WR_done)
+ wr_addr <= 0;
+ else if (WR)
+ wr_addr <= wr_addr + 7'd1;
+
+ always @(posedge txclk)
+ if(reset)
+ which_ram_wr <= 0;
+ else if (wr_done_int)
+ which_ram_wr <= which_ram_wr + 2'd1;
+
+ assign have_space = (nb_packets < 4);
+
+ // Reader side
+ always @(posedge txclk) dataout0 <= ram0[rd_addr];
+ always @(posedge txclk) dataout1 <= ram1[rd_addr];
+ always @(posedge txclk) dataout2 <= ram2[rd_addr];
+ always @(posedge txclk) dataout3 <= ram3[rd_addr];
+
+ assign dataout = (which_ram_rd[1]) ?
+ (which_ram_rd[0] ? dataout3 :
dataout2) :
+ (which_ram_rd[0] ? dataout1 :
dataout0);
+
+ reg next_packet;
+ assign rd_done_int = ((RD && (rd_addr == 7'd127)) || RD_done);
+
+ always @(posedge txclk)
+ if (reset)
+ rd_addr <= 0;
+ else if (RD_done)
+ rd_addr <= 0;
+ else if (RD) rd_addr <= rd_addr + 7'd1;
+
+ always @(posedge txclk)
+ if (reset)
+ begin
+ which_ram_rd <= 0;
+ next_packet <= 0;
+ end
+ else if (next_packet)
+ begin
+ which_ram_rd <= which_ram_rd + 2'd1;
+ next_packet <= 0;
+ end
+ else if (rd_done_int)
+ next_packet <= 1;
+
+ assign packet_waiting = (nb_packets > 0);
+
+ always @(posedge txclk)
+ if (reset)
+ nb_packets <= 0;
+ else if (wr_done_int & ~rd_done_int)
+ nb_packets <= nb_packets + 3'd1;
+ else if (rd_done_int & ~wr_done_int)
+ nb_packets <= nb_packets - 3'd1;
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-06 00:36:25 UTC (rev 5699)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -45,47 +45,36 @@
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
- wire [NUM_CHAN:0] WR_chan ;
- wire [NUM_CHAN:0] done_chan ;
+ wire [NUM_CHAN:0] chan_WR ;
+ wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
- wire [NUM_CHAN:0] underrun_chan ;
- wire [NUM_CHAN:0] txempty_chan ;
+ wire [NUM_CHAN:0] chan_underrun ;
+ wire [NUM_CHAN:0] chan_txempty ;
- /* Connections between tx_usb_fifo and its
- reader and writer */
- wire [31:0] tupf_fifodata_out ;
- wire [31:0] tupf_fifodata_in ;
- wire tupf_pkt_waiting ;
- wire tupf_rdreq ;
- wire tupf_write_enable ;
- wire [7:0] tupf_rdusedw ;
- wire [7:0] tupf_wrusedw ;
-
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
- wire [31:0] tdpf_fifodata [NUM_CHAN:0] ;
- wire tdpf_pkt_waiting [NUM_CHAN:0] ;
- wire tdpf_rdreq [NUM_CHAN:0] ;
- wire tdpf_skip [NUM_CHAN:0] ;
- wire [NUM_CHAN:0] tdpf_have_space ;
- wire txstrobe_chan [NUM_CHAN-1:0] ;
+ wire [31:0] chan_fifodata [NUM_CHAN:0] ;
+ wire chan_pkt_waiting [NUM_CHAN:0] ;
+ wire chan_rdreq [NUM_CHAN:0] ;
+ wire chan_skip [NUM_CHAN:0] ;
+ wire [NUM_CHAN:0] chan_have_space ;
+ wire chan_txstrobe [NUM_CHAN-1:0] ;
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
- assign have_space = (tupf_wrusedw < 127) ;
- assign tupf_pkt_waiting = (tupf_rdusedw >= 128) ;
+ assign have_space = chan_have_space[0] & chan_have_space[1];
/* TODO: Figure out how to write this genericly */
- assign tx_empty = txempty_chan[0] & txempty_chan[1] ;
- assign tx_underrun = underrun_chan[0] | underrun_chan[1] ;
- assign tx_i_0 = txempty_chan[0] ? 16'b0 : tx_i[0] ;
- assign tx_q_0 = txempty_chan[0] ? 16'b0 : tx_q[0] ;
- assign tx_i_1 = txempty_chan[1] ? 16'b0 : tx_i[1] ;
- assign tx_q_1 = txempty_chan[1] ? 16'b0 : tx_q[1] ;
+ assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
+ assign tx_underrun = chan_underrun[0] | chan_underrun[1] ;
+ assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
+ assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
+ assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
+ assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
@@ -95,27 +84,26 @@
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
- /*assign debugbus = {7'b0, have_space, tx_empty, WR,
tdpf_have_space[0],
- tdpf_have_space[1], bus_reset, reset, txempty_chan[0],
- txempty_chan[1]} ;*/
-
- wire [1:0]isfull;
- wire [1:0]a_in[1:0];
- wire [1:0]a_out[1:0];
-
- assign debugbus = {2'b0, a_in[0], a_out[0], isfull[0], 1'b0,
have_space, tupf_pkt_waiting, tdpf_pkt_waiting[0],
- WR, 1'b0,tdpf_have_space[0], reset, done_chan[0]} ;
+ assign debugbus = {7'b0, have_space, tx_empty, WR, chan_have_space[0],
+ chan_have_space[1], bus_reset, reset, chan_txempty[0],
+ chan_txempty[1]} ;
usb_fifo_writer tx_usb_packet_writer
- ( .reset (bus_reset),
- .usb_clock (usbclk),
- .write_enable_fx2 (WR),
- .bus_data (usbdata),
- .write_enable_fifo (tupf_write_enable),
- .write_data (tupf_fifodata_in)
+ (
+ .bus_reset (bus_reset),
+ .usbclk (usbclk),
+ .WR_fx2 (WR),
+ .usbdata (usbdata),
+ .reset (reset),
+ .txclk (txclk),
+ .WR_channel (chan_WR),
+ .WR_done_channel (chan_done),
+ .ram_data (tx_data_bus)
);
+
+
- fifo_1k tx_usb_packet_fifo
+ /*fifo_1k tx_usb_packet_fifo
( .aclr (reset),
.wrclk (usbclk),
.rdclk (txclk),
@@ -123,9 +111,9 @@
.wrreq (tupf_write_enable),
.q (tupf_fifodata_out),
.rdreq (tupf_rdreq),
- .wrfull (/* VOID */),
+ .wrfull (),
.wrusedw (tupf_wrusedw),
- .rdempty (/* VOID */),
+ .rdempty (),
.rdusedw (tupf_rdusedw)
);
@@ -140,24 +128,21 @@
.pkt_waiting (tupf_pkt_waiting),
.fifodata (tupf_fifodata_out),
.have_space_chan (tdpf_have_space)
- );
+ );*/
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
- data_packet_fifo tx_data_packet_fifo
+ channel_ram tx_data_packet_fifo
( .reset (reset),
- .clock (txclk),
- .ram_data_in (tx_data_bus),
- .write_enable (WR_chan[i]),
- .ram_data_out (tdpf_fifodata[i]),
- .pkt_waiting (tdpf_pkt_waiting[i]),
- .read_enable (tdpf_rdreq[i]),
- .pkt_complete (done_chan[i]),
- .skip_packet (tdpf_skip[i]),
- .isfull(isfull[i]),
- .usb_ram_packet_out(a_out[i]),
- .usb_ram_packet_in(a_in[i]),
- .have_space (tdpf_have_space[i])
+ .txclk (txclk),
+ .datain (tx_data_bus),
+ .WR (chan_WR[i]),
+ .WR_done (chan_done[i]),
+ .have_space (chan_have_space[i]),
+ .dataout (chan_fifodata[i]),
+ .packet_waiting (chan_pkt_waiting[i]),
+ .RD (chan_rdreq[i]),
+ .RD_done (chan_skip[i])
);
strobe_gen strobe_gen_chan
@@ -166,23 +151,23 @@
.enable (1'b1),
.rate (txstrobe_rate[i]),
.strobe_in (txstrobe),
- .strobe (txstrobe_chan[i])
+ .strobe (chan_txstrobe[i])
);
chan_fifo_reader tx_chan_reader
( .reset (reset),
.tx_clock (txclk),
.tx_strobe (txstrobe),
- .adc_time (time_counter),
+ .adc_time (32'd0),
.samples_format (4'b0),
.tx_q (tx_q[i]),
.tx_i (tx_i[i]),
- .underrun (underrun_chan[i]),
- .skip (tdpf_skip[i]),
- .rdreq (tdpf_rdreq[i]),
- .fifodata (tdpf_fifodata[i]),
- .pkt_waiting (tdpf_pkt_waiting[i]),
- .tx_empty (txempty_chan[i])
+ .underrun (chan_underrun[i]),
+ .skip (chan_skip[i]),
+ .rdreq (chan_rdreq[i]),
+ .fifodata (chan_fifodata[i]),
+ .pkt_waiting (chan_pkt_waiting[i]),
+ .tx_empty (chan_txempty[i])
);
end
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-06 00:36:25 UTC (rev 5699)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -1,48 +1,165 @@
-module usb_fifo_writer(reset, usb_clock, write_enable_fx2, bus_data,
- write_enable_fifo, write_data) ;
+module usb_fifo_writer
+ #(parameter BUS_WIDTH = 16,
+ parameter NUM_CHAN = 2,
+ parameter FIFO_WIDTH = 32)
+ (//FX2 Side
+ input bus_reset,
+ input usbclk,
+ input WR_fx2,
+ input [15:0]usbdata,
+
+ // TX Side
+ input reset,
+ input txclk,
+ output reg [NUM_CHAN:0] WR_channel,
+ output reg [FIFO_WIDTH-1:0] ram_data,
+ output reg [NUM_CHAN:0] WR_done_channel );
- /* Module parameters */
- parameter BUS_WIDTH = 16 ;
- parameter FIFO_WIDTH = 32 ;
-
- input wire reset ;
- input wire usb_clock ;
- input wire write_enable_fx2 ;
- input wire [BUS_WIDTH-1:0] bus_data ;
- output wire write_enable_fifo ;
- output wire [FIFO_WIDTH-1:0] write_data ;
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
- reg [BUS_WIDTH-1:0] write_data_delayed ;
-
+ reg [BUS_WIDTH-1:0] usbdata_delayed ;
reg writing ;
+ wire [FIFO_WIDTH-1:0] usbdata_packed ;
+ wire WR ;
+
+ //assign usbdata_packed = {usbdata_delayed, usbdata} ;
+ assign usbdata_packed = {usbdata, usbdata_delayed} ;
+ assign WR = ~word_complete & writing ;
- //assign write_data = {write_data_delayed, bus_data} ;
- assign write_data = {bus_data, write_data_delayed} ;
- assign write_enable_fifo = ~word_complete & writing ;
-
- always @(posedge usb_clock)
+ always @(posedge usbclk)
begin
- if (reset)
+ if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
- else if (write_enable_fx2)
+ else if (WR_fx2)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
- write_data_delayed <= bus_data ;
+ usbdata_delayed <= usbdata ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
- end
+ end
+
+ reg [31:0]usbdata_usbclk;
+ reg WR_usbclk;
+
+ always @(posedge usbclk)
+ begin
+ usbdata_usbclk <= usbdata_packed;
+ WR_usbclk <= WR;
+ end
+
+ reg [FIFO_WIDTH-1:0] usbdata_tx ;
+ reg WR_tx;
+ reg fresh;
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ begin
+ WR_tx <= 0;
+ fresh <= 1;
+ end
+ else if (WR_usbclk & ~WR_tx & fresh)
+ begin
+ usbdata_tx <= usbdata_usbclk ;
+ WR_tx <= 1 ;
+ end
+ else if (WR_usbclk & WR_tx)
+ begin
+ WR_tx <= 0;
+ fresh <= 0;
+ end
+ else if (WR_tx)
+ begin
+ WR_tx <= 0;
+ fresh <= 1;
+ end
+ else if (~WR_usbclk)
+ fresh <= 1;
+ end
+
+ reg [3:0]reader_state;
+ reg [4:0]channel ;
+ reg [9:0]pkt_length ;
+ reg [9:0]read_length ;
+
+ parameter IDLE = 4'd0;
+ parameter HEADER = 4'd1;
+ parameter FORWARD_HEADER = 4'd2;
+ parameter WAIT = 4'd3;
+ parameter FORWARD = 4'd4;
+ parameter WAIT2 = 4'd5;
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ begin
+ reader_state <= 0;
+ WR_channel <= 0;
+ WR_done_channel <= 0;
+ end
+ else
+ case (reader_state)
+ IDLE: begin
+ if (WR_tx)
+ reader_state <= HEADER;
+ end
+
+ HEADER: begin
+ channel <= (usbdata_tx[20:16]) ;
+ pkt_length <= usbdata_tx[8:0] + 9'd8;
+ read_length <= 10'd4 ;
+
+ WR_channel[usbdata_tx[20:16]] <= 1;
+ ram_data <= usbdata_tx;
+ reader_state <= WAIT;
+ end
+
+ FORWARD_HEADER: begin
+ WR_channel[channel] <= 1;
+ ram_data <= usbdata_tx;
+ reader_state <= WAIT;
+ end
+
+ WAIT: begin
+ WR_channel[channel] <= 0;
+
+ if (WR_tx)
+ begin
+ reader_state <= FORWARD;
+ end
+ end
+
+ FORWARD: begin
+ WR_channel[channel] <= 1;
+ ram_data <= usbdata_tx;
+ read_length <= read_length + 9'd4;
+
+ reader_state <= WAIT2;
+ end
+
+ WAIT2: begin
+ WR_channel[channel] <= 0;
+
+ if (read_length == 512)
+ reader_state <= IDLE;
+
+ if (WR_tx)
+ reader_state <= FORWARD;
+ end
+
+ endcase
+ end
endmodule
\ No newline at end of file
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-06 00:36:25 UTC (rev 5699)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-06 01:09:14 UTC (rev 5700)
@@ -414,4 +414,5 @@
set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
\ No newline at end of file
Modified:
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-06-06 00:36:25 UTC (rev 5699)
+++ gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -3,15 +3,14 @@
// Inputs
reg reset;
reg txclock;
-reg [31:0] data_bus;
+reg [31:0] datain;
reg [31:0] ttime;
reg WR;
reg adcclock;
reg debug;
-reg pkt_complete;
+reg WR_done;
wire [15:0] tx_q;
wire [15:0] tx_i;
-wire overrun;
wire underrun;
reg [15:0] i ;
@@ -24,6 +23,7 @@
wire [31:0] fifodata;
wire pkt_waiting;
wire tx_strobe;
+wire tx_empty;
chan_fifo_reader chan0 (
.reset(reset),
@@ -38,21 +38,22 @@
.tx_i(tx_i),
.underrun(underrun),
.samples_format(4'd0),
+ .tx_empty(tx_empty),
.tx_strobe(tx_strobe) );
// Channel fifo
- data_packet_fifo tx_data_fifo
+ channel_ram tx_data_fifo
( .reset(reset),
- .clock(txclock),
- .ram_data_in(data_bus),
- .write_enable(WR),
- .ram_data_out(fifodata),
- .pkt_waiting(pkt_waiting),
- .read_enable(rdreq),
- .pkt_complete(pkt_complete),
- .skip_packet(skip),
- .have_space()
+ .txclk(txclock),
+ .datain(datain),
+ .WR(WR),
+ .have_space(),
+ .dataout(fifodata),
+ .packet_waiting(pkt_waiting),
+ .RD(rdreq),
+ .WR_done(WR_done),
+ .RD_done(skip)
);
strobe_gen strobe_generator(
@@ -68,12 +69,12 @@
reset = 1;
adcclock = 0;
txclock = 0;
- data_bus = 0;
+ datain = 0;
WR = 0;
i = 0 ;
ttime = 0;
debug = 0;
- pkt_complete = 0;
+ WR_done = 0;
// Deassert the reset
#40 reset = 1'b0 ;
@@ -84,136 +85,12 @@
reset = 1'b0 ;
end
- //1
- repeat (20) begin
- @(posedge txclock)
- WR = 1'b1 ;
- // Payload len
- if (i == 0)
- data_bus = 32;
- // First 16 bits of timestamp
- else if (i == 1)
- data_bus = 1000;
- else
- data_bus = i ;
- i = i + 1 ;
-
- // Notify the fifo to increment the packet number
- if (i == 19)
- pkt_complete <= 1;
- end
+ send_packet(128, 16'd0, 32'hFFFFFFFF);
+ send_packet(3, 16'd0, 32'hFFFFFFFF);
+ send_packet(50, 16'd0, 32'hFFFFFFFF);
+ send_packet(100, 16'd0, 32'hFFFFFFFF);
- WR <= 0;
- i = 0;
- pkt_complete <= 0;
- //2
- repeat (12) begin
- @(posedge txclock)
- WR = 1'b1 ;
-
- //Payload len
- if (i == 0)
- data_bus = 16;
- //First 16 bits of timestamp
- else if (i == 1)
- data_bus = 1600;
- else
- data_bus = i ;
- i = i + 1 ;
-
- // Notify the fifo to increment the packet number
- if (i == 11)
- pkt_complete <= 1;
- end
-
- WR <= 0;
- i = 0;
- pkt_complete <= 0;
-
- @(posedge txclock)
- WR = 1'b0 ;
-
- //3
- repeat (12) begin
- @(posedge txclock)
- WR = 1'b1 ;
-
- //Payload len
- if (i == 0)
- data_bus = 16;
- //First 16 bits of timestamp
- else if (i == 1)
- data_bus = 1600;
- else
- data_bus = i ;
- i = i + 1 ;
-
- // Notify the fifo to increment the packet number
- if (i == 11)
- pkt_complete <= 1;
- end
-
- WR <= 0;
- i = 0;
- pkt_complete <= 0;
-
- @(posedge txclock)
- WR = 1'b0 ;
-
- //4
- repeat (12) begin
- @(posedge txclock)
- WR = 1'b1 ;
-
- //Payload len
- if (i == 0)
- data_bus = 16;
- //First 16 bits of timestamp
- else if (i == 1)
- data_bus = 1600;
- else
- data_bus = i ;
- i = i + 1 ;
-
- // Notify the fifo to increment the packet number
- if (i == 11)
- pkt_complete <= 1;
- end
-
- WR <= 0;
- i = 0;
- pkt_complete <= 0;
-
- @(posedge txclock)
- WR = 1'b0 ;
-
- //5
- repeat (12) begin
- @(posedge txclock)
- WR = 1'b1 ;
-
- //Payload len
- if (i == 0)
- data_bus = 16;
- //First 16 bits of timestamp
- else if (i == 1)
- data_bus = 1600;
- else
- data_bus = i ;
- i = i + 1 ;
-
- // Notify the fifo to increment the packet number
- if (i == 11)
- pkt_complete <= 1;
- end
-
- WR <= 0;
- i = 0;
- pkt_complete <= 0;
-
- @(posedge txclock)
- WR = 1'b0 ;
end
always@(posedge adcclock) begin
@@ -224,6 +101,36 @@
#5 txclock = ~txclock ;
always
- #1 adcclock = ~adcclock ;
+ #6 adcclock = ~adcclock ;
+
+task send_packet;
+ input [8:0]length;
+ input [15:0] channel;
+ input [31:0] timestamp;
+ begin
+ repeat (length) begin
+ @(posedge txclock)
+ WR = 1;
+ if (i == 0) datain = {channel, 7'd0,4*length - 8};
+ else if (i == 1) datain = timestamp;
+ else datain = i;//{16'hFFFF - i,i};
+ i = i + 1;
+ end
+
+ if (length < 128)
+ begin
+ @(posedge txclock)
+ WR_done = 1;
+ WR = 0;
+ @(posedge txclock)
+ WR_done = 0;
+ end
+ else
+ @(posedge txclock)
+ WR = 0;
+
+ i = 0;
+ end
+ endtask
endmodule
\ No newline at end of file
Added: gnuradio/branches/developers/thottelt/simulations/channel_ram_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/channel_ram_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/channel_ram_test.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -0,0 +1,105 @@
+module channel_ram_test();
+
+reg txclk, reset, WR, WR_done, RD, RD_done;
+reg [31:0] datain;
+wire [31:0] dataout;
+
+wire have_space;
+wire packet_waiting;
+
+
+reg [8:0] i;
+
+channel_ram ram
+ (
+ //System
+ .txclk(txclk),
+ .reset(reset),
+ // USB side
+ .datain(datain),
+ .WR(WR),
+ .WR_done(WR_done),
+ .have_space(have_space),
+ // Reader side
+ .dataout(dataout),
+ .RD(RD),
+ .RD_done(RD_done),
+ .packet_waiting(packet_waiting));
+
+ initial begin
+ reset = 1;
+ txclk = 0;
+ WR = 0;
+ WR_done = 0;
+ RD = 0;
+ RD_done = 0;
+ datain = 0;
+ i = 0;
+
+ #40 reset = 0;
+
+ send_packet(20);
+ send_packet(128);
+ send_packet(30);
+ send_packet(128);
+
+ read_packet(10);
+ read_packet(128);
+ read_packet(20);
+ read_packet(128);
+
+ end
+
+ always
+ #2 txclk = ~txclk;
+
+ task send_packet;
+ input [8:0]length;
+ begin
+ repeat (length) begin
+ @(posedge txclk)
+ WR = 1;
+ datain = i;
+ i = i + 1;
+ end
+
+ if (length < 128)
+ begin
+ @(posedge txclk)
+ WR_done = 1;
+ WR = 0;
+ @(posedge txclk)
+ WR_done = 0;
+ end
+ else
+ @(posedge txclk)
+ WR = 0;
+ end
+ endtask
+
+ task read_packet;
+ input [8:0]length;
+ begin
+ repeat (length) begin
+ @(posedge txclk)
+ RD = 1;
+ end
+ if (length < 128)
+ begin
+ @(posedge txclk)
+ RD_done = 1;
+ RD <= 0;
+ @(posedge txclk)
+ RD_done = 0;
+ end
+ else
+ @(posedge txclk)
+ RD = 0;
+ end
+ endtask
+
+ always @(posedge txclk)
+ if (RD)
+ $display(dataout);
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/simulations/channel_ram_test.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-06 00:36:25 UTC (rev 5699)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -83,11 +83,10 @@
bus_reset = 1;
i = 0;
- bus_reset = 0;
clear_status = 0;
channels = 0;
- #40 reset = 0;
+ #400 reset = 0;
bus_reset = 0;
if (file == 0)
@@ -139,8 +138,8 @@
end
always
- #5 usbclock = ~ usbclock;
+ #63 usbclock = ~ usbclock;
always
- #2 txclock = ~ txclock;
+ #48 txclock = ~ txclock;
endmodule
Added: gnuradio/branches/developers/thottelt/simulations/full_chip.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/full_chip.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/full_chip.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -0,0 +1,134 @@
+module full_chip();
+
+integer file, start, count, r;
+reg [7:0] packet [0:511];
+reg [7:0] i;
+
+reg master_clk;
+reg SLCK;
+reg SDI;
+reg SDO;
+reg SEN_FPGA;
+
+
+wire [13:0]tx_a;
+reg usbclk;
+
+wire clear_status = 0;
+
+reg WR, RD, OE;
+reg [15:0]usbdata;
+
+wire have_pkt_ready;
+wire have_space;
+
+wire [15:0]usbdata2;
+wire SDO2;
+
+assign usbdata2 = usbdata;
+assign SDO2 = SDO;
+
+usrp_inband_usb dut (
+ .MYSTERY_SIGNAL(),
+ .master_clk(master_clk),
+ .SCLK(1'b0),
+ .SDI(1'b0),
+ .SDO(SD02),
+ .SEN_FPGA(1'b0),
+
+ .FX2_1(clear_status),
+ .FX2_2(rx_overrun),
+ .FX2_3(tx_underrun),
+
+ .rx_a_a(),
+ .rx_b_a(),
+ .rx_a_b(),
+ .rx_b_b(),
+ .tx_a(tx_a),
+ .tx_b(),
+
+ .TXSYNC_A(),
+ .TXSYNC_B(),
+
+ .usbclk(usbclk),
+ .usbctl({OE, RD, WR}),
+ .usbrdy({have_pkt_rdy, have_space}),
+ .usbdata(usbdata2), // NB Careful, inout
+
+ .io_tx_a(),
+ .io_tx_b(),
+ .io_rx_a(),
+ .io_rx_b()
+ );
+
+
+
+initial begin
+ //file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
+ file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
+ start = 0;
+ count = 0;
+ usbclk = 0;
+ master_clk = 0;
+ WR = 0;
+ RD = 0;
+ OE = 0;
+ SDO = 2;
+ i = 0;
+
+ #40 i = 0;
+
+ if (file == 0)
+ begin
+ $display("cannot open specified file");
+ $finish;
+ end
+
+ while($feof(file) == 0)
+ begin
+ i = 0;
+
+ r = $fread(packet, file);
+ if (r != 512)
+ begin
+ $display("error while reading packets.dat");
+ //$finish;
+ end
+ else if (r == 0)
+ begin
+ $display("Done reading packets.dat");
+ $finish;
+ end
+ else if (r == 512)
+ begin
+ // Wait
+ i = 0;
+ while(have_space == 0)
+ begin
+ @(posedge usbclk)
+ i = 0;
+ end
+
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1;
+ usbdata = {packet[2*i+1],packet[2*i]};
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 0;
+ /*@(posedge usbclk)
+ WR = 0;*/
+ end
+ end
+
+ $display("Closing file...");
+ $fclose(file);
+end
+
+always
+ #4 usbclk = ~ usbclk;
+always
+ #1 master_clk = ~ master_clk;
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/simulations/full_chip.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-06
00:36:25 UTC (rev 5699)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-06
01:09:14 UTC (rev 5700)
@@ -131,7 +131,7 @@
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
-resolution = 1ps
+resolution = 1ns
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
@@ -140,7 +140,7 @@
UserTimeUnit = default
; Default run length
-RunLength = 100 ps
+RunLength = 0 ns
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
@@ -243,159 +243,55 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 76
-Project_File_0 = Z:/wc/inband/usrp/fpga/sdr_lib/setting_reg.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726985 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
69 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = Z:/wc/inband/usrp/fpga/sdr_lib/master_control.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
56 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = Z:/wc/inband/usrp/fpga/sdr_lib/ext_fifo.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
53 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_3 = Z:/wc/simulations/fake_tx_chain.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = Z:/wc/inband/usrp/fpga/megacells/clk_doubler.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727112 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = Z:/wc/inband/usrp/fpga/models/bustri.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726992 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/ram16.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726978 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
60 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = Z:/wc/inband/usrp/fpga/megacells/dspclkpll.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = Z:/wc/inband/usrp/fpga/sdr_lib/bidir_reg.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
42 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = Z:/wc/inband/usrp/fpga/models/fifo.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726992 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 31
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = Z:/wc/inband/usrp/fpga/sdr_lib/ddc.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
50 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = ./chan_fifo_readers_test.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180832728 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = Z:/wc/inband/usrp/fpga/megacells/accum32.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_14 = Z:/wc/inband/usrp/fpga/megacells/add32.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_15 = Z:/wc/inband/usrp/fpga/models/fifo_1k.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 35
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_16 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
72 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_17 = ./usb_packet_fifo_test.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_18 = Z:/wc/inband/usrp/fpga/sdr_lib/master_control_multi.v
-Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
57 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = Z:/wc/inband/usrp/fpga/sdr_lib/gen_sync.v
-Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
54 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_20 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180923485 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 32
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
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vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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Z:/wc/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 75
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 37
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180922343 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180922563 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 34
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_36 = Z:/wc/inband/usrp/fpga/sdr_lib/cordic.v
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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-Project_File_39 = Z:/wc/inband/usrp/fpga/sdr_lib/serial_io.v
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 36
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
67 dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_47 = Z:/wc/inband/usrp/fpga/sdr_lib/sign_extend.v
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726985 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 33
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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-Project_File_50 = Z:/wc/inband/usrp/fpga/models/ssram.v
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 39
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
63 dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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Level} last_compile 1180726978 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
59 dont_compile 0 cover_expr 0 cover_stmt 0
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cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180969005 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_65 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_65 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180922278 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_66 = Z:/wc/inband/usrp/fpga/sdr_lib/dpram.v
-Project_File_P_66 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
51 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_67 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_67 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_68 = Z:/wc/inband/usrp/fpga/models/pll.v
-Project_File_P_68 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 38
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_69 = Z:/wc/inband/usrp/fpga/sdr_lib/atr_delay.v
-Project_File_P_69 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
41 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_70 = Z:/wc/simulations/full_chip.v
-Project_File_P_70 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180972912 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_71 = Z:/wc/inband/usrp/fpga/sdr_lib/setting_reg_masked.v
-Project_File_P_71 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
70 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_72 = Z:/wc/inband/usrp/fpga/sdr_lib/phase_acc.v
-Project_File_P_72 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
58 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_73 = Z:/wc/inband/usrp/fpga/megacells/bustri.v
-Project_File_P_73 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727112 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_74 = Z:/wc/inband/usrp/fpga/megacells/mylpm_addsub.v
-Project_File_P_74 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
28 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_75 = Z:/wc/inband/usrp/fpga/sdr_lib/cic_decim.v
-Project_File_P_75 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
44 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Files_Count = 24
+Project_File_0 = Z:/wc/simulations/fake_tx_chain.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ./chan_fifo_readers_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181087600 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = ./usb_packet_fifo_test.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181008809 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = ./tx_buffer_test.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = Z:/wc/simulations/channel_ram_test.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181060194 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
23 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181058450 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = Z:/wc/simulations/data_packet_fifo_test.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 =
Z:/wc/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 21
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180995228 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181083437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_15 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
18 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = ./fake_fx2_test.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_17 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_18 = ./usb_fifo_reader_test.v
+Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_19 = ./strobe_gen_test.v
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_20 = ./usb_fifo_writer_test.v
+Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181081874 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_21 = ./fake_fx2.v
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181088101 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181073478 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_23 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -425,6 +321,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 0}
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/fake_fx2_test.v 0 0}
{Z:/wc/simulations/fake_tx_chain.v 0 0} {Z:/wc/simulations/full_chip.v 0 1}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_writer.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
2007-06-06 00:36:25 UTC (rev 5699)
+++ gnuradio/branches/developers/thottelt/simulations/usb_fifo_writer_test.v
2007-06-06 01:09:14 UTC (rev 5700)
@@ -1,52 +1,81 @@
module usb_fifo_writer_test() ;
-reg reset ;
-reg usb_clock ;
-reg write_enable_fx2 ;
-reg [15:0]bus_data ;
+reg bus_reset ;
+reg usbclk ;
+reg WR_fx2 ;
+reg [15:0]usbdata ;
-wire write_enable_fifo ;
-wire [31:0]write_data ;
+reg reset;
+reg txclk;
+wire [2:0] WR_channel;
+wire [31:0]ram_data ;
+wire [2:0]WR_done_channel;
-reg [7:0] i ;
+reg [15:0] i ;
-usb_fifo_writer test_writer(
- .reset ( reset ),
- .usb_clock ( usb_clock ),
- .write_enable_fx2 ( write_enable_fx2 ),
- .bus_data ( bus_data ),
- .write_enable_fifo ( write_enable_fifo ),
- .write_data ( write_data )
-) ;
+usb_fifo_writer writer (//FX2 Side
+ .bus_reset(bus_reset),
+ .usbclk(usbclk),
+ .WR_fx2(WR_fx2),
+ .usbdata(usbdata),
+
+ // TX Side
+ .reset(reset),
+ .txclk(txclk),
+ .WR_channel(WR_channel),
+ .ram_data(ram_data),
+ .WR_done_channel(WR_done_channel) );
initial begin
+ bus_reset = 1;
reset = 1 ;
- usb_clock = 0 ;
- write_enable_fx2 = 0 ;
- bus_data = 0 ;
+ usbclk = 0 ;
+ txclk = 0;
+ WR_fx2 = 0 ;
+ usbdata = 0 ;
i = 0 ;
#40 reset = 0 ;
+ bus_reset = 0;
+ send_packet(100, 16'd0, 32'hFFFFFFFF);
+ send_packet(30, 16'd0, 32'hFFFFFFFF);
+ send_packet(120, 16'd0, 32'hFFFFFFFF);
+ send_packet(170, 16'd0, 32'hFFFFFFFF);
- repeat (10) begin
- @(posedge usb_clock)
- write_enable_fx2 = 1'b1 ;
- bus_data = i ;
- i = i + 1 ;
- end
-
- @(posedge usb_clock)
- write_enable_fx2 = 1'b0 ;
-
end
+always
+ #13 usbclk = ~usbclk ;
+
+ always
+ #3 txclk = ~txclk ;
-always
- #5 usb_clock = ~usb_clock ;
+ task send_packet;
+ input [8:0]length;
+ input [15:0] channel;
+ input [31:0] timestamp;
+ begin
+ repeat (256) begin
+ @(posedge usbclk)
+ WR_fx2 = 1;
+ if (i == 0) usbdata = channel;
+ else if (i == 1) usbdata = length;
+ else if (i == 2) usbdata = timestamp[31:16];
+ else if (i == 3) usbdata = timestamp[15:0];
+ else usbdata = i;//{16'hFFFF - i,i};
+ i = i + 1;
+ end
+
+ @(posedge usbclk)
+ WR_fx2 = 0;
+
+ i = 0;
+ end
+ endtask
endmodule
\ No newline at end of file
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- [Commit-gnuradio] r5700 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations,
thottelt <=