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[Commit-gnuradio] r5519 - gnuradio/branches/developers/matt/u2f/control_
From: |
matt |
Subject: |
[Commit-gnuradio] r5519 - gnuradio/branches/developers/matt/u2f/control_lib |
Date: |
Tue, 22 May 2007 19:27:32 -0600 (MDT) |
Author: matt
Date: 2007-05-22 19:27:31 -0600 (Tue, 22 May 2007)
New Revision: 5519
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
Log:
write side appears to work, with the possible exception of the last line in the
fifo
Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
2007-05-23 00:33:17 UTC (rev 5518)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
2007-05-23 01:27:31 UTC (rev 5519)
@@ -15,8 +15,8 @@
// Buffer Interface
output en_o,
- output reg we_o,
- output [8:0] addr_o,
+ output we_o,
+ output reg [8:0] addr_o,
output [31:0] dat_to_buf,
input [31:0] dat_from_buf,
@@ -38,9 +38,6 @@
// FIXME do we want to be able to interleave reads and writes?
// FIXME do we want rd_ack or rd_req?
- reg [8:0] addr;
- assign addr_o = addr;
-
wire rd_en, wr_en;
assign dat_to_buf = wr_dat_i;
@@ -57,7 +54,7 @@
always @(posedge clk)
if(rst)
begin
- addr <= 0;
+ addr_o <= 0;
state <= IDLE;
end
else
@@ -65,36 +62,52 @@
IDLE :
if(read_go)
begin
- addr <= firstline;
+ addr_o <= firstline;
state <= PRE_READ;
end
else if(write_go)
begin
- addr <= firstline;
+ addr_o <= firstline;
state <= WRITING;
end
PRE_READ :
begin
state <= READING;
- addr <= addr + 1;
+ addr_o <= addr_o + 1;
end
READING :
if(rd_read_i)
begin
- addr <= addr + 1;
- if(addr == lastline + 9'd1)
+ addr_o <= addr_o + 1;
+ if(addr_o == lastline + 9'd1)
state <= IDLE;
end
WRITING :
- state <= IDLE;
+ begin
+ if(wr_write_i)
+ begin
+ addr_o <= addr_o + 1;
+ if(addr_o == lastline)
+ state <= IDLE;
+ end
+ if(wr_done_i)
+ state <= IDLE;
+ end
+
endcase // case(state)
+ // FIXME read side ignores rd_done_i for now
+
assign rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i);
- assign rd_empty_o = (state == IDLE);
+ assign rd_empty_o = (state != READING) && (state != PRE_READ);
assign rd_ready_o = (state == READING);
+
+ assign wr_en = (state == WRITING) && wr_write_i; // IF this is a timing
problem, we could always enable when in this state
+ assign we_o = (state == WRITING) && wr_write_i; // IF this is a timing
problem, we could always write when in this state
+ assign wr_full_o = (state != WRITING);
+ assign wr_ready_o = (state == WRITING);
-
endmodule // fifo_int
Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
2007-05-23 00:33:17 UTC (rev 5518)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
2007-05-23 01:27:31 UTC (rev 5519)
@@ -19,18 +19,23 @@
wire rd_ready_o, rd_empty_o;
wire rd_done_i = 0;
reg rd_read_i;
+
+ reg [31:0] wr_dat_i;
+ reg wr_write_i=0;
+ wire wr_ready_o, wr_full_o;
+ wire wr_done_i = 0;
fifo_int fifo_int
(.clk(clk),.rst(rst),
.firstline(firstline),.lastline(lastline),
- .step(step),.read_go(read_go),.write_go(),.done(),
+ .step(step),.read_go(read_go),.write_go(write_go),.done(),
// Buffer Interface
.en_o(en),.we_o(we),.addr_o(addr),
.dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
// Write FIFO Interface
- .wr_dat_i(), .wr_write_i(), .wr_done_i(), .wr_ready_o(), .wr_full_o(),
+ .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i),
.wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o),
// Read FIFO Interface
.rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i),
.rd_ready_o(rd_ready_o), .rd_empty_o(rd_empty_o)
@@ -96,12 +101,81 @@
@(posedge clk);
@(posedge clk);
end
+
+ firstline <= 123;
+ lastline <= 137;
+ write_go <= 1;
+ wr_dat_i <= 193;
+ @(posedge clk);
+ write_go <= 0;
+ repeat (20)
+ begin
+ wr_write_i <= 1;
+ @(posedge clk);
+ wr_dat_i <= wr_dat_i + 1;
+ end
+ wr_write_i <= 0;
+
+ @(posedge clk);
+ firstline <= 120;
+ @(posedge clk);
+ lastline <= 140;
+ @(posedge clk);
+ read_go <= 1;
+ @(posedge clk);
+ read_go <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ repeat (25)
+ begin
+ rd_read_i <= 1;
+ @(posedge clk);
+ end
+ rd_read_i <= 0;
+
+ firstline <= 505;
+ lastline <= 2;
+ write_go <= 1;
+ wr_dat_i <= 235;
+ @(posedge clk);
+ write_go <= 0;
+ repeat (20)
+ begin
+ wr_write_i <= 1;
+ @(posedge clk);
+ wr_dat_i <= wr_dat_i + 1;
+ end
+ wr_write_i <= 0;
+
+ @(posedge clk);
+ firstline <= 500;
+ @(posedge clk);
+ lastline <= 5;
+ @(posedge clk);
+ read_go <= 1;
+ @(posedge clk);
+ read_go <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ repeat (25)
+ begin
+ rd_read_i <= 1;
+ @(posedge clk);
+ end
+ rd_read_i <= 0;
+
$finish;
end
always @(posedge clk)
if(rd_read_i == 1'd1)
- $display("FIFO OUT %d, FIFO RDY %d, FIFO EMPTY ",rd_dat_o, rd_ready_o,
rd_empty_o);
+ $display("FIFO READ %d, FIFO RDY %d, FIFO EMPTY ",rd_dat_o, rd_ready_o,
rd_empty_o);
+
+ always @(posedge clk)
+ if(wr_write_i == 1'd1)
+ $display("FIFO WRITE %d, FIFO RDY %d, FIFO FULL ",wr_dat_i, wr_ready_o,
wr_full_o);
initial begin
$dumpfile("fifo_int_tb.vcd");
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