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[Commit-gnuradio] r5508 - in gnuradio/branches/developers/jcorgan/sar/gr
From: |
jcorgan |
Subject: |
[Commit-gnuradio] r5508 - in gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga: lib toplevel |
Date: |
Mon, 21 May 2007 00:25:53 -0600 (MDT) |
Author: jcorgan
Date: 2007-05-21 00:25:53 -0600 (Mon, 21 May 2007)
New Revision: 5508
Added:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
Log:
Work in progress.
Modified: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-05-21 06:24:27 UTC (rev 5507)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-05-21 06:25:53 UTC (rev 5508)
@@ -50,12 +50,15 @@
output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
- // Configuration from host
- wire [31:0] mag, freq, phase;
- setting_reg #(`FR_USER_0)
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag));
- setting_reg #(`FR_USER_1)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq));
- setting_reg #(`FR_USER_2)
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phase));
+ wire [15:0] mag;
+ wire [31:0] freq;
+ wire [31:0] phs;
+ sar_control controller
+ (.clk_i(clk_i),.rst_i(rst_i),.ena_i(1'b1),
+ .s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i),
+ .mag_o(mag),.freq_o(freq),.phs_o(phs));
+
sar_tx transmitter
( .clk_i(clk_i),.rst_i(tx_rst_i),.ena_i(tx_enable_i),
.mag_i(mag),.freq_i(freq),.phs_i(phase),
Added:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
(rev 0)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
2007-05-21 06:25:53 UTC (rev 5508)
@@ -0,0 +1,46 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2007 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+
+module sar_control(clk_i,rst_i,ena_i,saddr_i,sdata_i,s_strobe_i,
+ mag_o, freq_o, phs_o);
+
+ // System interface
+ input clk_i; // Master clock @ 64 MHz
+ input rst_i; // Master reset
+ input ena_i; // Module level enable
+ input [6:0] saddr_i; // Configuration bus address
+ input [31:0] sdata_i; // Configuration bus data
+ input s_strobe_i; // Configuration bus write
+
+ // Configuration outputs
+ output [15:0] mag_o;
+ output [31:0] freq_o;
+ output [31:0] phs_o;
+
+ // Configuration from host
+ setting_reg #(`FR_USER_0)
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag_o));
+ setting_reg #(`FR_USER_1)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq_o));
+ setting_reg #(`FR_USER_2)
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phs_o));
+
+endmodule // sar_control
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-05-21 06:24:27 UTC (rev 5507)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-05-21 06:25:53 UTC (rev 5508)
@@ -372,6 +372,7 @@
set_global_assignment -name VERILOG_FILE dacpll.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
+set_global_assignment -name VERILOG_FILE ../lib/sar_control.v
set_global_assignment -name VERILOG_FILE ../lib/sar_rx.v
set_global_assignment -name VERILOG_FILE ../lib/sar_tx.v
set_global_assignment -name VERILOG_FILE ../lib/sar.v
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