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[Commit-gnuradio] r5493 - gnuradio/branches/developers/matt/u2f/control_
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r5493 - gnuradio/branches/developers/matt/u2f/control_lib |
|
Date: |
Thu, 17 May 2007 21:54:41 -0600 (MDT) |
Author: matt
Date: 2007-05-17 21:54:41 -0600 (Thu, 17 May 2007)
New Revision: 5493
Added:
gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
gnuradio/branches/developers/matt/u2f/control_lib/setting_reg.v
gnuradio/branches/developers/matt/u2f/control_lib/settings_bus.v
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes.v
Log:
progress
Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-05-18 03:48:29 UTC (rev 5492)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -6,9 +6,10 @@
// provides access to all 8 buffers, and also controls the connections
// between the ports and the buffers, allocating them as needed.
-// wb_adr is 13 bits --
-// bit 12 control (1) or data (1)
-// bits 11:9 select which buffer
+// wb_adr is 16 bits --
+// bits 13:11 select which buffer
+// bits 10:2 select line in buffer
+// bits 1:0 are unused (32-bit access only)
module buffer_pool
(input wb_clk_i,
@@ -20,45 +21,33 @@
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
-
+ output wb_rty_o,
+
input stream_clk,
+ input stream_rst,
+
// Write Interfaces
- input [31:0] din_0,
- input write_0,
- input done_0,
- output wr_rdy_0,
+ input [31:0] wr0_dat_i,
+ input wr0_write_i,
+ output wr0_ready_o,
+ output wr0_done_o,
- input [31:0] din_1,
- input write_1,
- input done_1,
- output wr_rdy_1,
-
- input [31:0] din_2,
- input write_2,
- input done_2,
- output wr_rdy_2,
-
// Read Interfaces
- output [31:0] dout_0,
- output rd_rdy_0,
- input read_0,
-
- output [31:0] dout_1,
- output rd_rdy_1,
- input read_1,
-
- output [31:0] dout_2,
- output rd_rdy_2,
- input read_2
+ output [31:0] rd0_dat_o,
+ input rd0_read_i,
+ output rd0_ready_o,
+ output rd0_done_o
+
);
assign wb_err_o = 1'b0; // Unused for now
+ assign wb_rty_o = 1'b0; // Unused for now
wire [7:0] sel_a;
wire [31:0] buf0_outa, buf1_outa, buf2_outa, buf3_outa, buf4_outa,
buf5_outa, buf6_outa, buf7_outa;
wire [2:0] which_buf = wb_adr_i[13:11]; // address 15:14 selects the
buffer pool
- wire [8:0] buf_addr = wb_adr_i[10:2]; // ignore address 1:0
+ wire [8:0] buf_addr = wb_adr_i[10:2]; // ignore address 1:0, 32-bit
access only
wire buf0_dir, buf1_dir, buf2_dir, buf3_dir,
buf4_dir, buf5_dir, buf6_dir, buf7_dir;
@@ -69,63 +58,66 @@
wire [8:0] buf0_end, buf1_end, buf2_end, buf3_end,
buf4_end, buf5_end, buf6_end, buf7_end;
- decoder_3_8 dec(.sel(wb_adr_i[11:9]),.res(sel_a));
+ decoder_3_8 dec(.sel(which_buf),.res(sel_a));
wire [31:0] b0di, b0do, b1di, b1do, b2di, b2do, b3di, b3do,
b4di, b4do, b5di, b5do, b6di, b6do, b7di, b7do;
- mux_32_4 m0i(buf0_sel, din_0, din_1, din_2, 32'd0, b0di);
- mux_32_4 m1i(buf1_sel, din_0, din_1, din_2, 32'd0, b1di);
- mux_32_4 m2i(buf2_sel, din_0, din_1, din_2, 32'd0, b2di);
- mux_32_4 m3i(buf3_sel, din_0, din_1, din_2, 32'd0, b3di);
- mux_32_4 m4i(buf4_sel, din_0, din_1, din_2, 32'd0, b4di);
- mux_32_4 m5i(buf5_sel, din_0, din_1, din_2, 32'd0, b5di);
- mux_32_4 m6i(buf6_sel, din_0, din_1, din_2, 32'd0, b6di);
- mux_32_4 m7i(buf7_sel, din_0, din_1, din_2, 32'd0, b7di);
+ wire b0enb, b1enb, b2enb, b3enb, b4enb, b5enb, b6enb, b7enb;
+ wire b0web, b1web, b2web, b3web, b4web, b5web, b6web, b7web;
+
+ wire [8:0] b0a, b1a, b2a, b3a, b4a, b5a, b6a, b7a;
buffer_2k buf_0
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[0]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf0_outa),
- .clkb(stream_clk),.enb(1),.web(),.addrb(b0a),.dib(b0di),.dob(b0do));
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf0_outa),
+
.clkb(stream_clk),.enb(b0enb),.web(b0web),.addrb(b0a),.dib(b0di),.dob(b0do));
+
+ fifo_int fifo_int_0
+ (.clk(stream_clk),.rst(dsp_rst),.firstline(),.lastline(),.step(),
+
.en_o(b0enb),.we_o(b0web),.addr_o(b0a),.dat_to_buf(b0di),.dat_from_buf(b0do),
+
.wr_dat_i(wr0_dat_i),.wr_write_i(wr0_write_i),.wr_ready_o(wr0_ready_o),//.wr_done_o(wr0_done_o),
+
.rd_dat_o(rd0_dat_o),.rd_read_i(rd0_read_i),.rd_ready_o(rd0_ready_o)//.rd_done_o(rd0_done_o)
+ );
buffer_2k buf_1
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[1]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf1_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf1_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b1a),.dib(b1di),.dob(b1do));
buffer_2k buf_2
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[2]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf2_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf2_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b2a),.dib(b2di),.dob(b2do));
buffer_2k buf_3
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[3]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf3_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf3_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b3a),.dib(b3di),.dob(b3do));
buffer_2k buf_4
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[4]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf4_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf4_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b4a),.dib(b4di),.dob(b4do));
buffer_2k buf_5
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[5]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf5_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf5_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b5a),.dib(b5di),.dob(b5do));
buffer_2k buf_6
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[6]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf6_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf6_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b6a),.dib(b6di),.dob(b6do));
buffer_2k buf_7
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[7]),.wea(wb_we_i),
- .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf7_outa),
+ .addra(buf_addr),.dia(wb_dat_i),.doa(buf7_outa),
.clkb(stream_clk),.enb(1),.web(),.addrb(b7a),.dib(b7di),.dob(b7do));
always @(posedge wb_clk_i)
if(wb_stb_i)
- case(wb_adr_i)
+ case(which_buf)
3'd0 : wb_dat_o <= buf0_outa;
3'd1 : wb_dat_o <= buf1_outa;
3'd2 : wb_dat_o <= buf2_outa;
@@ -134,7 +126,7 @@
3'd5 : wb_dat_o <= buf5_outa;
3'd6 : wb_dat_o <= buf6_outa;
3'd7 : wb_dat_o <= buf7_outa;
- endcase // case(wb_adr_i)
+ endcase // case(which_buf)
always @(posedge wb_clk_i)
wb_ack_o <= wb_stb_i;
Added: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -0,0 +1,66 @@
+
+
+// FIFO Interface to the 2K buffer RAMs
+
+module fifo_int
+ (// Control Interface
+ input clk,
+ input rst,
+ input [8:0] firstline,
+ input [8:0] lastline,
+ input [3:0] step,
+ input go,
+ input read,
+ output done,
+
+ // Buffer Interface
+ output en_o,
+ output reg we_o,
+ output [8:0] addr_o,
+ output [31:0] dat_to_buf,
+ input [31:0] dat_from_buf,
+
+ // Write FIFO Interface
+ input [31:0] wr_dat_i,
+ input wr_write_i,
+ input wr_done_i,
+ output wr_ready_o,
+ output wr_full_o,
+
+ // Read FIFO Interface
+ output [31:0] rd_dat_o,
+ input rd_read_i,
+ input rd_done_i,
+ output rd_ready_o,
+ output rd_empty_o
+ );
+
+ // FIXME do we want to be able to interleave reads and writes?
+ // FIXME do we want rd_ack or rd_req?
+
+ reg [8:0] wr_addr, rd_addr;
+
+ assign dat_to_buf = wr_dat_i;
+ assign rd_dat_o = dat_from_buf;
+ assign en_o = 1'b1;
+
+ always @(posedge clk)
+ if(go)
+ wr_addr <= firstline;
+ else if(wr_write_i)
+ begin
+ we_o <= 1'b1;
+ wr_addr <= wr_addr + step;
+ end
+ else
+ we_o <= 1'b0;
+
+/*
+ always @(posedge clk)
+ if(rd_read_i)
+ if(rd_addr == lastline)
+ rd_done_o <= 1'b1;
+ else
+ */
+
+endmodule // fifo_int
Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
2007-05-18 03:48:29 UTC (rev 5492)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_reader.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -3,8 +3,9 @@
#(parameter rate=4)
(input clk,
input [31:0] data_in,
- input ready,
- output read
+ output read_o
+ input ready_i,
+ input done_i
);
reg [7:0] state = 0;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
2007-05-18 03:48:29 UTC (rev 5492)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_writer.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -3,9 +3,9 @@
#(parameter rate=4)
(input clk,
output [31:0] data_out,
- output write,
- input done,
- input ready
+ output write_o,
+ input ready_i,
+ input done_i
);
reg [7:0] state = 0;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes.v 2007-05-18
03:48:29 UTC (rev 5492)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes.v 2007-05-18
03:54:41 UTC (rev 5493)
@@ -120,9 +120,9 @@
always @(posedge clk)
rcv_comma_ret <= rcv_comma;
-
+
always @(posedge ser_rx_clk)
- rcv_error <= (ser_rkmsb & ser_rklsb & ((ser_r[7:0] == LOS)||(ser_r[7:0]
== ERROR));
+ rcv_error <= (ser_rkmsb & ser_rklsb & ((ser_r[7:0] == LOS)||(ser_r[7:0]
== ERROR)));
always @(posedge clk)
rcv_error_ret <= rcv_error;
Added: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -0,0 +1,76 @@
+
+// SERDES Interface
+
+// LS-Byte is sent first, MS-Byte is second
+// Invalid K Codes
+// K0.0 000-00000 Error detected
+// K31.7 111-11111 Loss of input signal
+
+// Valid K Codes
+// K28.0 000-11100
+// K28.1 001-11100 Alternate COMMA?
+// K28.2 010-11100
+// K28.3 011-11100
+// K28.4 100-11100
+// K28.5 101-11100 Standard COMMA?
+// K28.6 110-11100
+// K28.7 111-11100 Bad COMMA?
+// K23.7 111-10111
+// K27.7 111-11011
+// K29.7 111-11101
+// K30.7 111-11110
+
+module serdes_rx
+ (input clk,
+ input rst,
+
+ // RX HW Interface
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ output [31:0] fifo_data_o,
+ output fifo_wr_o,
+ input fifo_ready_i,
+ input fifo_done_i
+ );
+
+ localparam COMMA = 8'b101_11100; // K28.5
+ //localparam IDLE = 8'b001_11100; // K28.1
+ localparam PKT_START = 8'b110_11100; // K28.6
+ localparam PKT_END = 8'b100_11100; // K28.4
+ localparam LOS = 8'b111_11111; // K31.7
+ localparam ERROR = 8'b000_00000; // K0.0
+
+ assign ser_tx_clk = clk;
+
+ localparam IDLE = 3'd0;
+ localparam START = 3'd1;
+ localparam RUN = 3'd2;
+ localparam RESTART = 3'd3;
+ localparam ON_ERROR = 3'd4;
+
+ reg [2:0] state, next_state;
+
+ reg [7:0] counter;
+
+ reg rcv_comma, rcv_comma_ret, rcv_error, rcv_error_ret;
+
+ always @(posedge ser_rx_clk)
+ rcv_comma <= (ser_rkmsb & (ser_r[15:8] == COMMA)) ||
+ (ser_rklsb & (ser_r[7:0] == COMMA));
+
+ always @(posedge clk)
+ rcv_comma_ret <= rcv_comma;
+
+ always @(posedge ser_rx_clk)
+ rcv_error <= (ser_rkmsb & ser_rklsb & ((ser_r[7:0] == LOS)||(ser_r[7:0]
== ERROR)));
+
+ always @(posedge clk)
+ rcv_error_ret <= rcv_error;
+
+ assign din = {counter,rcv_comma,state[2:0],ser_rkmsb,ser_rklsb,ser_r[15:0]};
+
+endmodule // serdes_rx
+
Added: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -0,0 +1,103 @@
+
+// SERDES Interface
+
+// LS-Byte is sent first, MS-Byte is second
+// Invalid K Codes
+// K0.0 000-00000 Error detected
+// K31.7 111-11111 Loss of input signal
+
+// Valid K Codes
+// K28.0 000-11100
+// K28.1 001-11100 Alternate COMMA?
+// K28.2 010-11100
+// K28.3 011-11100
+// K28.4 100-11100
+// K28.5 101-11100 Standard COMMA?
+// K28.6 110-11100
+// K28.7 111-11100 Bad COMMA?
+// K23.7 111-10111
+// K27.7 111-11011
+// K29.7 111-11101
+// K30.7 111-11110
+
+module serdes_tx
+ (input clk,
+ input rst,
+
+ // TX HW Interface
+ output ser_tx_clk,
+ output reg [15:0] ser_t,
+ output reg ser_tklsb,
+ output reg ser_tkmsb,
+
+ // TX Stream Interface
+ input [31:0] fifo_data_i,
+ output fifo_read_o,
+ input fifo_ready_i,
+ input fifo_done_i
+ );
+
+ localparam COMMA = 8'b101_11100; // K28.5
+ //localparam IDLE = 8'b001_11100; // K28.1
+ localparam PKT_START = 8'b110_11100; // K28.6
+ localparam PKT_END = 8'b100_11100; // K28.4
+ localparam LOS = 8'b111_11111; // K31.7
+ localparam ERROR = 8'b000_00000; // K0.0
+
+ assign ser_tx_clk = clk;
+
+ localparam IDLE = 3'd0;
+ localparam START = 3'd1;
+ localparam RUN1 = 3'd2;
+ localparam RUN2 = 3'd3;
+ localparam DONE = 3'd4;
+
+ reg [2:0] state, next_state;
+
+ // FIXME Implement sending of flow control, possibly also idles if data
not ready net
+
+ always @(posedge clk)
+ if(rst)
+ begin
+ state <= IDLE;
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,COMMA,COMMA};
+ end
+ else
+ case(state)
+ IDLE :
+ begin
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,COMMA,COMMA};
+ if(fifo_ready_i)
+ state <= START;
+ end
+ START :
+ begin
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,PKT_START,PKT_START};
+ state <= RUN1;
+ end
+ RUN1 :
+ begin
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_i[15:0]};
+ state <= RUN2;
+ end
+ RUN2 :
+ begin
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_i[31:16]};
+ if(fifo_done_i)
+ state <= DONE;
+ else
+ state <= RUN1;
+ end
+ DONE :
+ begin
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,PKT_END,PKT_END};
+ state <= IDLE;
+ end
+ default
+ state <= IDLE;
+ endcase // case(state)
+
+ assign fifo_read_o = (state == START) || ((state == RUN2) & ~fifo_done_i);
+
+endmodule // serdes_tx
+
Copied: gnuradio/branches/developers/matt/u2f/control_lib/setting_reg.v (from
rev 5191, gnuradio/branches/developers/matt/u2f/sdr_lib/setting_reg.v)
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/setting_reg.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/setting_reg.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -0,0 +1,23 @@
+
+
+module setting_reg
+ #(parameter my_addr = 0)
+ (input clk, input rst, input strobe, input wire [7:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+
+ always @(posedge clk)
+ if(rst)
+ begin
+ out <= #1 32'd0;
+ changed <= #1 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= #1 in;
+ changed <= #1 1'b1;
+ end
+ else
+ changed <= #1 1'b0;
+
+endmodule // setting_reg
Added: gnuradio/branches/developers/matt/u2f/control_lib/settings_bus.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/settings_bus.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/settings_bus.v
2007-05-18 03:54:41 UTC (rev 5493)
@@ -0,0 +1,42 @@
+
+// Grab settings off the wishbone bus, send them out to our simpler bus on the
fast clock
+
+module settings_bus
+ #(parameter AWIDTH=16, parameter DWIDTH=32)
+ (input wb_clk,
+ input wb_rst,
+ input [AWIDTH-1:0] wb_adr_i,
+ input [DWIDTH-1:0] wb_dat_i,
+ input wb_stb_i,
+ input wb_we_i,
+ output wb_ack_o,
+ input sys_clk,
+ output reg strobe,
+ output reg [7:0] addr,
+ output reg [31:0] data);
+
+ reg stb_int;
+
+ always @(posedge wb_clk)
+ if(wb_rst)
+ begin
+ stb_int <= 1'b0;
+ addr <= 8'd0;
+ data <= 32'd0;
+ end
+ else if(wb_we_i & wb_stb_i)
+ begin
+ stb_int <= 1'b1;
+ addr <= wb_adr_i[9:2];
+ data <= wb_dat_i;
+ end
+ else
+ stb_int <= 1'b0;
+
+ assign wb_ack_o = stb_int;
+
+ always @(posedge sys_clk)
+ strobe <= stb_int;
+
+endmodule // settings_bus
+
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