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[Commit-gnuradio] r5255 - in gnuradio/branches/developers/matt/u2f/top:
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5255 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_fpga |
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Date: |
Mon, 7 May 2007 19:20:56 -0600 (MDT) |
Author: matt
Date: 2007-05-07 19:20:56 -0600 (Mon, 07 May 2007)
New Revision: 5255
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Log:
intermediate changes...
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-05-07 23:31:04 UTC (rev 5254)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-05-08 01:20:56 UTC (rev 5255)
@@ -27,8 +27,9 @@
module u2_basic
(
// Clocks
- input clk_fpga,
- input aux_clk,
+ input dsp_clk,
+ input wb_clk,
+ output clock_ready,
input clk_to_mac,
input pps_in,
@@ -138,16 +139,18 @@
inout [15:0] io_rx
);
- wire dsp_clk, wb_clk, clock_ready, ram_loader_done;
+ wire ram_loader_done;
wire ram_loader_rst, processor_rst, wb_rst, dsp_rst;
wire [7:0] sysctrl_dbg;
+
+ assign debug = {{dac_a},{dac_b}};
- assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,processor_rst,wb_rst,dsp_rst},
-
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
- {sysctrl_dbg},
- {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
- assign debug_clk[0] = aux_clk;
- assign debug_clk[1] = clk_fpga;
+// assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,processor_rst,wb_rst,dsp_rst},
+ //
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+ // {sysctrl_dbg},
+ // {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
+ assign debug_clk[0] = wb_clk;
+ assign debug_clk[1] = dsp_clk;
parameter dw = 32; // Data bus width
parameter aw = 16; // Address bus width, for byte addressibility, 16 =
64K byte memory space
@@ -171,8 +174,8 @@
//////////////////////////////////////////////////////////////////////////////////////////
// System Controller, handles reset and clocks
- system_control sysctrl (.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
- .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
+ system_control sysctrl (.aux_clk_i(wb_clk),.clk_fpga_i(dsp_clk),
+ .dsp_clk_o(),.wb_clk_o(),
.ram_loader_rst_o(ram_loader_rst),.processor_rst_o(processor_rst),
.wb_rst_o(wb_rst),.dsp_rst_o(dsp_rst),
.ram_loader_done_i(ram_loader_done),.clock_ready_i(clock_ready),
@@ -331,10 +334,6 @@
.s7_cab_o(s7_cab),.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
);
- assign s5_ack = 1'b0;
- assign s5_err = 1'b0;
- assign s5_rty = 1'b0;
- assign s5_dat_i = 32'd0;
assign s6_ack = 1'b0;
assign s6_err = 1'b0;
assign s6_rty = 1'b0;
@@ -343,7 +342,37 @@
assign s7_err = 1'b0;
assign s7_rty = 1'b0;
assign s7_dat_i = 32'd0;
+
+
+ // DSP
+ reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+ reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1,
adc_ovf_b_reg2;
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg1 <= adc_a;
+ adc_a_reg2 <= adc_a_reg1;
+ adc_b_reg1 <= adc_b;
+ adc_b_reg2 <= adc_b_reg1;
+ adc_ovf_a_reg1 <= adc_ovf_a;
+ adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+ adc_ovf_b_reg1 <= adc_ovf_b;
+ adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+ end // always @ (posedge dsp_clk)
+
+ dsp_core dsp_core (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+ .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_adr_i(s5_adr),
+ .wb_sel_i(s5_sel),.wb_dat_i(s5_dat_o),
+ .wb_dat_o(s5_dat_i),.wb_ack_o(s5_ack),
+ .dsp_clk(dsp_clk),.dsp_rst(dsp_rst),
+ .adc_a(adc_a_reg2),.adc_ovf_a(adc_ovf_a_reg2),
+ .adc_b(adc_b_reg2),.adc_ovf_b(adc_ovf_b_reg2),
+ .dac_a(dac_a),.dac_b(dac_b) );
+
+ assign s5_err = 1'b0;
+ assign s5_rty = 1'b0;
+
+
endmodule // u2_basic
// Local Variables:
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
2007-05-07 23:31:04 UTC (rev 5254)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
2007-05-08 01:20:56 UTC (rev 5255)
@@ -302,13 +302,11 @@
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
-NET "clk_fpga_n" TNM_NET = "clk_fpga_n";
-TIMESPEC "TS_clk_fpga_n" = PERIOD "clk_fpga_n" 10 ns HIGH 50 %;
-NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
-TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns LOW 50 %;
+NET "dsp_clk" TNM_NET = "dsp_clk";
+TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
-NET "u2_basic/sysctrl/half_clk" TNM_NET = "u2_basic/sysctrl/half_clk";
-TIMESPEC "TS_u2_basic_sysctrl_half_clk" = PERIOD "u2_basic/sysctrl/half_clk"
"TS_clk_fpga_n" * 2;
+NET "wb_clk" TNM_NET = "wb_clk";
+TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 2;
NET "cpld_clk" TNM_NET = "cpld_clk";
TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-05-07 23:31:04 UTC (rev 5254)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-05-08 01:20:56 UTC (rev 5255)
@@ -158,7 +158,11 @@
);
// FPGA-specific pins connections
- wire clk_fpga;
+ wire aux_clk = RAM_CE1n; // FIXME Hacked on with Blue Wire
+ wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
+
+ wire clk_fpga, dsp_clk, clk_div2, dcm_out, wb_clk, clock_ready;
+
IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
@@ -170,10 +174,54 @@
OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ // Handle Clocks
+ DCM DCM_INST (.CLKFB(dsp_clk),
+ .CLKIN(clk_fpga),
+ .DSSEN(0),
+ .PSCLK(0),
+ .PSEN(0),
+ .PSINCDEC(0),
+ .RST(RST_IN),
+ .CLKDV(clk_div2),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(dcm_out),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST.FACTORY_JF = 16'h8080;
+ defparam DCM_INST.PHASE_SHIFT = 0;
+ defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+ BUFGMUX wbclk_BUFGMUX (.I0(aux_clk),
+ .I1(clk_div2),
+ .S(clock_ready),
+ .O(wb_clk));
+
+ BUFG dspclk_BUFG (.I(dcm_out),
+ .O(dsp_clk));
+
+
+ // I2C -- Don't use external transistors for open drain, the FPGA
implements this
IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
-
- // Don't use external transistors for open drain, the FPGA implements this
assign SCL_force = 1'b0;
assign SDA_force = 1'b0;
@@ -182,9 +230,6 @@
assign led1 = ~led1_int;
assign led2 = ~led2_int;
- wire aux_clk = RAM_CE1n; // FIXME Hacked on with Blue Wire
- wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
-
// SPI
wire miso, mosi, sclk_int;
assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
@@ -199,8 +244,9 @@
(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
- u2_basic u2_basic(.clk_fpga (clk_fpga),
- .aux_clk (aux_clk),
+ u2_basic u2_basic(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
.clk_to_mac (clk_to_mac),
.pps_in (pps_in),
.led1 (led1_int),
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- [Commit-gnuradio] r5255 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_fpga,
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