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[Commit-gnuradio] r5247 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5247 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
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Date: |
Sat, 5 May 2007 14:50:56 -0600 (MDT) |
Author: thottelt
Date: 2007-05-05 14:50:56 -0600 (Sat, 05 May 2007)
New Revision: 5247
Removed:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
Log:
usb_fifo_reader/writer work again, in the process of fixing chan_fifo*
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-05 18:57:54 UTC (rev 5246)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-05 20:50:56 UTC (rev 5247)
@@ -1,38 +1,42 @@
module chan_fifo_reader
- ( input reset,
- input tx_clock,
- input tx_strobe,
- input [31:0]adc_clock,
- input [3:0] samples_format,
- input [15:0] fifodata,
- input pkt_waiting,
- output reg rdreq,
- output reg skip,
- output reg [15:0]tx_q,
- output reg [15:0]tx_i,
- output reg overrun,
- output reg underrun) ;
+ ( reset, tx_clock, tx_strobe, adc_time, samples_format,
+ fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
+ overrun, underrun ) ;
+ input wire reset ;
+ input wire tx_clock ;
+ input wire tx_strobe ;
+ input wire [31:0] adc_time ;
+ input wire [3:0] samples_format ;
+ input wire [31:0] fifodata ;
+ input wire pkt_waiting ;
+ output reg rdreq ;
+ output reg skip ;
+ output reg [15:0] tx_q ;
+ output reg [15:0] tx_i ;
+ output reg overrun ;
+ output reg underrun ;
+
// Should not be needed if adc clock rate < tx clock rate
- `define JITTER 5
+ `define JITTER 5
//Samples format
// 16 bits interleaved complex samples
- `define QI16 4'b0
+ `define QI16 4'b0
// States
- `define IDLE 4'd0
- `define READ 4'd1
- `define HEADER1 4'd2
- `define HEADER2 4'd3
- `define TIMESTAMP1 4'd4
- `define TIMESTAMP2 4'd5
- `define WAIT 4'd6
- `define WAITSTROBE 4'd7
- `define SENDWAIT 4'd8
- `define SEND 4'd9
- `define FEED 4'd10
- `define DISCARD 4'd11
+ `define IDLE 4'd0
+ `define READ 4'd1
+ `define HEADER1 4'd2
+ `define HEADER2 4'd3
+ `define TIMESTAMP1 4'd4
+ `define TIMESTAMP2 4'd5
+ `define WAIT 4'd6
+ `define WAITSTROBE 4'd7
+ `define SENDWAIT 4'd8
+ `define SEND 4'd9
+ `define FEED 4'd10
+ `define DISCARD 4'd11
// State registers
reg[3:0] reader_state;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-05-05 18:57:54 UTC (rev 5246)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-05-05 20:50:56 UTC (rev 5247)
@@ -1,21 +1,22 @@
module data_packet_fifo
( input reset,
input clock,
- input [15:0]ram_data_in,
+ input [31:0]ram_data_in,
input write_enable,
output reg have_space,
- output reg [15:0]ram_data_out,
+ output reg [31:0]ram_data_out,
output reg pkt_waiting,
input read_enable,
input pkt_complete,
input skip_packet) ;
/* Some parameters for usage later on */
- parameter DATA_WIDTH = 16 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter FIFO_DEPTH = 128 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
- reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+ reg [DATA_WIDTH-1:0] usb_ram [FIFO_DEPTH*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7:0] usb_ram_offset_out ;
@@ -36,9 +37,9 @@
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain >= usb_ram_aout)
- pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+ pkt_waiting <= usb_ram_ain - usb_ram_aout >= FIFO_DEPTH;
else
- pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
256;
+ pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
FIFO_DEPTH;
end
// Check if there is room
@@ -49,9 +50,9 @@
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
- have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS -
1);
+ have_space <= (usb_ram_ain - usb_ram_aout) <= FIFO_DEPTH *
(NUM_PACKETS - 1);
else
- have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
+ have_space <= (usb_ram_aout - usb_ram_ain) >= FIFO_DEPTH;
end
/* RAM Write Address process */
@@ -70,7 +71,7 @@
end
else if( write_enable )
begin
- if (usb_ram_offset_in == 8'b11111111)
+ if (usb_ram_offset_in == 7'b1111111)
begin
usb_ram_offset_in <= 0;
usb_ram_packet_in <= usb_ram_packet_in + 1;
@@ -107,7 +108,7 @@
usb_ram_offset_out <= 0 ;
end
else if(read_enable) begin
- if( usb_ram_offset_out == 8'b11111111 )
+ if( usb_ram_offset_out == 7'b1111111 )
begin
usb_ram_offset_out <= 0 ;
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-05-05 18:57:54 UTC (rev 5246)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-05-05 20:50:56 UTC (rev 5247)
@@ -1,98 +1,107 @@
module tx_buffer_inband
- ( input usbclk,
- input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
- input reset, // standard DSP-side reset
- input [15:0] usbdata,
- input wire WR,
- output wire have_space,
- output reg tx_underrun,
- input wire [3:0] channels,
- output [15:0] tx_i_0,
- output [15:0] tx_q_0,
- output [15:0] tx_i_1,
- output [15:0] tx_q_1,
- //NOT USED
- output reg [15:0] tx_i_2,
- output reg [15:0] tx_q_2,
- output reg [15:0] tx_i_3,
- output reg [15:0] tx_q_3,
- input txclk,
- input txstrobe,
- input clear_status,
- output wire tx_empty,
- output [11:0] debugbus
- );
-
- wire [15:0] tx_data_bus;
-
- wire WR_chan_0;
- wire chan_0_done;
- wire OR0;
- wire UR0;
+ ( usbclk, bus_reset, reset, usbdata, WR, have_space,
+ tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
+ tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe,
+ clear_status, tx_empty, debugbus
+ );
+
+ parameter NUM_CHAN = 2 ;
+
+ input wire usbclk ;
+ input wire bus_reset ; // Used here for the 257-Hack to
fix the FX2 bug
+ input wire reset ; // standard DSP-side reset
+ input wire [15:0] usbdata ;
+ input wire WR ;
+ input wire txclk ;
+ input wire txstrobe ;
+ /* Not used yet */
+ input wire [3:0] channels ;
+ input wire clear_status ;
+
+ output wire have_space ;
+ output reg tx_underrun ;
+ output wire tx_empty ;
+ output wire [15:0] tx_i_0 ;
+ output wire [15:0] tx_q_0 ;
+ output wire [15:0] tx_i_1 ;
+ output wire [15:0] tx_q_1 ;
+ /* Not used yet */
+ output wire [11:0] debugbus ;
+ output wire [15:0] tx_i_2 ;
+ output wire [15:0] tx_q_2 ;
+ output wire [15:0] tx_i_3 ;
+ output wire [15:0] tx_q_3 ;
- wire WR_chan_1;
- wire chan_1_done;
- wire OR1;
- wire UR1;
+ /* These will eventually be external register */
+ reg [31:0] time_counter ;
+ reg [7:0] txstrobe_rate_0 ;
+ reg [7:0] txstrobe_rate_1 ;
- // NOT USED yet
- wire WR_cmd;
- wire cmd_done;
+ /* Connections between tx_usb_fifo_reader and
+ cnannel/command processing blocks */
+ wire [31:0] tx_data_bus ;
+ wire [NUM_CHAN:0] WR_chan ;
+ wire [NUM_CHAN:0] done_chan ;
+ wire [NUM_CHAN:0] overrun_chan ;
+ wire [NUM_CHAN:0] underrun_chan ;
- //EXTERNAL REGISTER
- //TODO: increment it
- reg [31:0] time_counter;
- reg [7:0] txstrobe_rate_0;
- reg [7:0] txstrobe_rate_1;
+ /* Connections between tx_usb_fifo and its
+ reader and writer */
+ wire [31:0] tupf_fifodata_out ;
+ wire [31:0] tupf_fifodata_in ;
+ wire tupf_pkt_waiting ;
+ wire tupf_rdreq ;
+ wire tupf_write_enable ;
+ wire tupf_wrfull ;
+ wire [7:0] tupf_usedw ;
+ /* Conections between tx_data_packet_fifo and
+ its reader + strobe generator */
+ wire [31:0] tdpf_fifodata_0;
+ wire tdpf_pkt_waiting_0;
+ wire tdpf_rdreq_0;
+ wire tdpf_skip_0;
+ wire tdpf_have_space_0;
+ wire txstrobe_chan_0;
+
+ assign have_space = ~tupf_wrfull ;
+ assign tupf_pkt_waiting = (tupf_usedw >= 128);
- //Usb block
- wire [15:0] tupf_fifodata;
- wire tupf_pkt_waiting;
- wire tupf_rdreq;
- wire tupf_skip;
- wire tupf_have_space;
+ usb_fifo_writer tx_usb_packet_writer
+ ( .reset (reset),
+ .usb_clock (usbclk),
+ .write_enable_fx2 (WR),
+ .bus_data (usbdata),
+ .write_enable_fifo (tupf_write_enable),
+ .write_data (tupf_fifodata_in)
+ );
- usb_packet_fifo2 tx_usb_packet_fifo
- ( .reset (reset),
- .usb_clock (usbclk),
- .fpga_clock (txclk),
- .write_data (usbdata),
- .write_enable (WR),
- .read_data (tupf_fifodata),
- .pkt_waiting (tupf_pkt_waiting),
- .read_enable (tupf_rdreq),
- .skip_packet (tupf_skip),
- .have_space (tupf_have_space),
- .tx_empty (tx_empty)
+ fifo_1k tx_usb_packet_fifo
+ ( .aclr (reset),
+ .wrclk (usbclk),
+ .rdclk (txclk),
+ .data (tupf_fifodata_in),
+ .wrreq (tupf_write_enable),
+ .q (tupf_fifodata_out),
+ .rdreq (tupf_rdreq),
+ .wrfull (tupf_wrfull),
+ .rdempty (),
+ .rdusedw (tupf_usedw)
);
- usb_fifo_reader tx_usb_packet_reader (
- .reset(reset),
- .tx_clock(txclk),
- .tx_data_bus(tx_data_bus),
- .WR_chan_0(WR_chan_0),
- .WR_chan_1(WR_chan_1),
- .WR_cmd(WR_cmd),
- .chan_0_done(chan_0_done),
- .chan_1_done(chan_1_done),
- .cmd_done(cmd_done),
- .rdreq(tupf_rdreq),
- .skip(tupf_skip),
- .pkt_waiting(tupf_pkt_waiting),
- .fifodata(tupf_fifodata)
- );
+ usb_fifo_reader tx_usb_packet_reader
+ (
+ .reset (reset),
+ .tx_clock (txclk),
+ .tx_data_bus (tx_data_bus),
+ .WR_chan (WR_chan),
+ .done_chan (done_chan),
+ .rdreq (tupf_rdreq),
+ .pkt_waiting (tupf_pkt_waiting),
+ .fifodata (tupf_fifodata_out)
+ );
-
- //Channel 0 block
- wire [15:0] tdpf_fifodata_0;
- wire tdpf_pkt_waiting_0;
- wire tdpf_rdreq_0;
- wire tdpf_skip_0;
- wire tdpf_have_space_0;
- wire txstrobe_chan_0;
-
- data_packet_fifo tx_data_packet_fifo_0
+ /*data_packet_fifo tx_data_packet_fifo_0
( .reset(reset),
.clock(txclk),
.ram_data_in(tx_data_bus),
@@ -105,7 +114,7 @@
.have_space(tdpf_have_space_0)
);
- strobe_gen strobe_gen_0
+ strobe_gen strobe_gen_0
( .clock(txclk),
.reset(reset),
.enable(1'b1),
@@ -114,7 +123,7 @@
.strobe(txstrobe_chan_0)
);
- chan_fifo_reader tx_chan_0_reader (
+ chan_fifo_reader tx_chan_0_reader (
.reset(reset),
.tx_clock(txclk),
.tx_strobe(txstrobe),
@@ -132,7 +141,7 @@
);
- //Channel 1 block
+ Channel 1 block
wire [15:0] tdpf_fifodata_1;
wire tdpf_pkt_waiting_1;
wire tdpf_rdreq_1;
@@ -177,7 +186,7 @@
.rdreq(tdpf_rdreq_1),
.fifodata(tdpf_fifodata_1),
.pkt_waiting(tdpf_pkt_waiting_1)
- );
+ );*/
endmodule // tx_buffer
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-05-05 18:57:54 UTC (rev 5246)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-05-05 20:50:56 UTC (rev 5247)
@@ -1,16 +1,16 @@
module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset,
- rdreq, skip, done_chan, WR_chan, tx_data_bus);
+ rdreq, done_chan, WR_chan, tx_data_bus);
/* Module parameters */
parameter NUM_CHAN = 2 ;
parameter WIDTH = 32 ;
+ parameter PKT_SIZE = 512 ;
input wire tx_clock ;
input wire reset ;
input wire [WIDTH-1:0] fifodata ;
input wire pkt_waiting ;
output reg rdreq ;
- output reg skip ;
output reg [NUM_CHAN:0] done_chan ;
output reg [NUM_CHAN:0] WR_chan ;
output reg [WIDTH-1:0] tx_data_bus ;
@@ -44,7 +44,6 @@
reader_state <= `IDLE ;
reader_next_state <= `IDLE ;
rdreq <= 0 ;
- skip <= 0 ;
WR_chan <= {NUM_CHAN+1{1'b0}} ;
done_chan <= {NUM_CHAN+1{1'b0}} ;
end
@@ -56,6 +55,7 @@
`IDLE:
begin
reader_next_state <= pkt_waiting ? `WAIT :
`IDLE ;
+ done_chan <= {NUM_CHAN+1{1'b0}} ;
rdreq <= pkt_waiting ;
end
@@ -71,8 +71,8 @@
/* Read header fields */
channel <= (fifodata & 32'h1F0000) ;
- pkt_length <= (fifodata & 16'h1FF) + 4 ;
- read_length <= 9'd0 ;
+ pkt_length <= (fifodata & 16'h1FF) + 8 ;
+ read_length <= 9'd4 ;
/* Forward data */
case (channel)
@@ -91,9 +91,7 @@
// If end of payload...
if (read_length == pkt_length)
begin
- reader_next_state <= `SKIP_REST ;
- /* If the packet is 512 bytes, don't skip */
- skip <= pkt_length < 506 ;
+ reader_next_state <= rdreq ? `SKIP_REST : `IDLE ;
/* Data pushing done */
WR_chan <= {NUM_CHAN+1{1'b0}} ;
@@ -106,19 +104,23 @@
default: done_chan[0] <= 1 ;
endcase
end
- else if (read_length == pkt_length - 4)
- rdreq <= 0 ;
+ if (read_length == PKT_SIZE - 8)
+ rdreq <= 0;
+
/* Forward data */
tx_data_bus <= fifodata ;
end
`SKIP_REST:
begin
- reader_next_state <= pkt_waiting ? `READ_HEADER
: `IDLE ;
- done_chan <= {NUM_CHAN+1{1'b0}} ;
- rdreq <= pkt_waiting ;
- skip <= 0 ;
+ read_length <= read_length + 4;
+ done_chan <= {NUM_CHAN+1{1'b0}} ;
+
+ if (read_length == PKT_SIZE - 4)
+ reader_next_state <= `IDLE ;
+ else if (read_length == PKT_SIZE - 8)
+ rdreq <= 0 ;
end
default:
Deleted:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-05
18:57:54 UTC (rev 5246)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-05
20:50:56 UTC (rev 5247)
@@ -246,40 +246,40 @@
Project_Files_Count = 18
Project_File_0 = ./strobe_gen_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = ./usb_fifo_writer_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234317 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = ./usb_packet_fifo2_test.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177718026 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178390642 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = ./fake_fx2_test.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = ./usb_fifo_writer_test.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234317 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = ./fake_fx2.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_9 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = ./fake_fx2.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178393232 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178396255 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = ./chan_fifo_readers_test.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232565 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ./usb_packet_fifo_test.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_13 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = ./tx_buffer_test.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177348942 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_15 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397015 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = ./usb_fifo_reader_test.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177713127 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -309,6 +309,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/usb_packet_fifo2_test.v
0 0} {Z:/wc/simulations/fake_fx2.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 0 0}
{Z:/wc/simulations/usb_writer_test.v 0 1}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/usb_fifo_reader_test.v
0 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-05-05 18:57:54 UTC (rev 5246)
+++ gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-05-05 20:50:56 UTC (rev 5247)
@@ -14,28 +14,36 @@
wire have_space ;
wire tx_empty ;
-
+wire [31:0]to_write_data ;
+wire [7:0] tupf_usedw ;
+wire wrfull;
reg [15:0] i ;
wire [31:0] fifodata;
wire rdreq;
-wire skip;
wire pkt_waiting;
-// FIFO
- usb_packet_fifo2 usb_fifo (
- .reset (reset),
- .usb_clock (usb_clock),
- .fpga_clock (tx_clock),
- .have_space (have_space),
- .pkt_waiting (pkt_waiting),
- .tx_empty (tx_empty),
- .write_enable (WR),
- .read_enable (rdreq),
- .skip_packet (skip),
- .read_data (fifodata),
- .write_data (usb_data)
- ) ;
+usb_fifo_writer tx_usb_packet_writer
+ ( .reset (reset),
+ .usb_clock (usb_clock),
+ .write_enable_fx2 (WR),
+ .bus_data (usb_data),
+ .write_enable_fifo (tupf_write_enable),
+ .write_data (to_write_data)
+ );
+
+ fifo_1k tx_usb_packet_fifo
+ ( .aclr (reset),
+ .wrclk (usb_clock),
+ .rdclk (tx_clock),
+ .data (to_write_data),
+ .wrreq (tupf_write_enable),
+ .q (fifodata),
+ .rdreq (rdreq),
+ .wrfull (wrfull),
+ .rdempty (),
+ .rdusedw (tupf_usedw)
+ );
usb_fifo_reader reader (
.reset(reset),
@@ -45,10 +53,11 @@
.done_chan(done_chan),
.fifodata(fifodata),
.pkt_waiting(pkt_waiting),
- .rdreq(rdreq),
- .skip(skip)
+ .rdreq(rdreq)
);
+assign pkt_waiting = (tupf_usedw >= 128) ;
+assign have_space = ~wrfull ;
// Initialize Inputs
initial begin
@@ -100,7 +109,7 @@
usb_data = 1;
else if (i == 1)
// payload size
- usb_data = 504;
+ usb_data = 500;
else
usb_data = i ;
i = i + 1 ;
Deleted:
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
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- [Commit-gnuradio] r5247 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations,
thottelt <=