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e1000 patch for grub 0.93
|
From: |
James Scott |
|
Subject: |
e1000 patch for grub 0.93 |
|
Date: |
Fri, 14 Mar 2003 23:57:21 +0000 |
|
User-agent: |
Mozilla/5.0 (Windows; U; Win98; en-US; rv:1.3) Gecko/20030312 |
I enclose a patch which adds e1000 support to grub 0.93, using code from
the etherboot sources.
Ta
James Scott
diff -rc2P -x '*~' grub-0.93/configure grub-0.93-e1000/configure
*** grub-0.93/configure 2002-11-29 20:28:30.000000000 +0000
--- grub-0.93-e1000/configure 2003-03-14 16:59:30.000000000 +0000
***************
*** 858,861 ****
--- 858,862 ----
--enable-eepro enable Etherexpress Pro/10 driver
--enable-eepro100 enable Etherexpress Pro/100 driver
+ --enable-e1000 enable e1000 driver
--enable-epic100 enable SMC 83c170 EPIC/100 driver
--enable-3c507 enable 3Com507 driver
***************
*** 4822,4825 ****
--- 4823,4836 ----
fi
+ # Check whether --enable-e1000 or --disable-e1000 was given.
+ if test "${enable_e1000+set}" = set; then
+ enableval="$enable_e1000"
+
+ fi;
+ if test "x$enable_e1000" = xyes; then
+ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_E1000=1"
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS e1000.o"
+ fi
+
# Check whether --enable-epic100 or --disable-epic100 was given.
if test "${enable_epic100+set}" = set; then
***************
*** 5287,5291 ****
-
ac_config_files="$ac_config_files Makefile stage1/Makefile stage2/Makefile
docs/Makefile lib/Makefile util/Makefile grub/Makefile netboot/Makefile
util/grub-image util/grub-install util/grub-md5-crypt util/grub-terminfo"
cat >confcache <<\_ACEOF
--- 5298,5301 ----
diff -rc2P -x '*~' grub-0.93/configure.in grub-0.93-e1000/configure.in
*** grub-0.93/configure.in 2002-11-29 20:12:08.000000000 +0000
--- grub-0.93-e1000/configure.in 2003-03-14 15:40:20.000000000 +0000
***************
*** 355,358 ****
--- 355,365 ----
fi
+ AC_ARG_ENABLE(e1000,
+ [ --enable-e1000 enable e1000 driver])
+ if test "x$enable_e1000" = xyes; then
+ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_E1000=1"
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS e1000.o"
+ fi
+
AC_ARG_ENABLE(epic100,
[ --enable-epic100 enable SMC 83c170 EPIC/100 driver])
***************
*** 624,628 ****
AC_SUBST(ASFLAGS)
-
dnl Output.
AC_OUTPUT([Makefile stage1/Makefile stage2/Makefile docs/Makefile \
--- 631,634 ----
diff -rc2P -x '*~' grub-0.93/netboot/cards.h grub-0.93-e1000/netboot/cards.h
*** grub-0.93/netboot/cards.h 2002-01-02 21:56:40.000000000 +0000
--- grub-0.93-e1000/netboot/cards.h 2003-03-14 12:49:15.000000000 +0000
***************
*** 76,79 ****
--- 76,84 ----
#endif
+ #ifdef INCLUDE_E1000
+ extern struct nic *e1000_probe(struct nic *, unsigned short *
+ PCI_ARG(struct pci_device *));
+ #endif
+
#ifdef INCLUDE_EPIC100
extern struct nic *epic100_probe(struct nic *, unsigned short *
diff -rc2P -x '*~' grub-0.93/netboot/config.c grub-0.93-e1000/netboot/config.c
*** grub-0.93/netboot/config.c 2002-04-20 01:43:10.000000000 +0100
--- grub-0.93-e1000/netboot/config.c 2003-03-14 16:44:52.000000000 +0000
***************
*** 32,36 ****
#undef INCLUDE_PCI
! #if defined(INCLUDE_NS8390) || defined(INCLUDE_EEPRO100) ||
defined(INCLUDE_LANCE) || defined(INCLUDE_EPIC100) || defined(INCLUDE_TULIP) ||
defined(INCLUDE_OTULIP) || defined(INCLUDE_3C90X) || defined(INCLUDE_3C595) ||
defined(INCLUDE_RTL8139) || defined(INCLUDE_VIA_RHINE) ||
defined(INCLUDE_W89C840) || defined(INCLUDE_DAVICOM) || defined(INCLUDE_SIS900)
|| defined(INCLUDE_NATSEMI) || defined(INCLUDE_TLAN)
/* || others later */
# define INCLUDE_PCI
--- 32,36 ----
#undef INCLUDE_PCI
! #if defined(INCLUDE_NS8390) || defined(INCLUDE_EEPRO100) ||
defined(INCLUDE_E1000) || defined(INCLUDE_LANCE) || defined(INCLUDE_EPIC100) ||
defined(INCLUDE_TULIP) || defined(INCLUDE_OTULIP) || defined(INCLUDE_3C90X) ||
defined(INCLUDE_3C595) || defined(INCLUDE_RTL8139) ||
defined(INCLUDE_VIA_RHINE) || defined(INCLUDE_W89C840) ||
defined(INCLUDE_DAVICOM) || defined(INCLUDE_SIS900) || defined(INCLUDE_NATSEMI)
|| defined(INCLUDE_TLAN)
/* || others later */
# define INCLUDE_PCI
***************
*** 126,129 ****
--- 126,141 ----
"Intel EtherExpressPro100 82562EM", 0, 0, 0, 0},
#endif
+ #ifdef INCLUDE_E1000
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542,
+ "Intel E1000 82542",0,0,0,0},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER,
+ "Intel E1000 82543GC_FIBER",0,0,0,0},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER,
+ "Intel E1000 82543GC_COPPER",0,0,0,0},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER,
+ "Intel E1000 82544EI_COPPER",0,0,0,0},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_CREB,
+ "Intel E1000 82544GC_CREB",0,0,0,0},
+ #endif
#ifdef INCLUDE_EPIC100
{ PCI_VENDOR_ID_SMC, PCI_DEVICE_ID_SMC_EPIC100,
***************
*** 284,287 ****
--- 296,306 ----
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82562, eepro100_probe },
# endif /* INCLUDE_EEPRO100 */
+ # ifdef INCLUDE_E1000
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542, e1000_probe },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER, e1000_probe },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER,e1000_probe },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER,e1000_probe },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_CREB, e1000_probe },
+ # endif /* INCLUDE_E1000 */
# ifdef INCLUDE_EPIC100
{ PCI_VENDOR_ID_SMC, PCI_DEVICE_ID_SMC_EPIC100, epic100_probe },
***************
*** 399,402 ****
--- 418,424 ----
{ "EEPRO100", eepro100_probe, pci_ioaddrs },
#endif
+ #ifdef INCLUDE_E1000
+ { "E1000", e1000_probe, pci_ioaddrs },
+ #endif
#ifdef INCLUDE_EPIC100
{ "EPIC100", epic100_probe, pci_ioaddrs },
diff -rc2P -x '*~' grub-0.93/netboot/e1000.c grub-0.93-e1000/netboot/e1000.c
*** grub-0.93/netboot/e1000.c 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000.c 2003-03-14 15:30:46.000000000 +0000
***************
*** 0 ****
--- 1,434 ----
+ #ifdef ALLMULTI
+ #error multicast support is not yet implemented
+ #endif
+ /**************************************************************************
+ Etherboot - BOOTP/TFTP Bootstrap Program
+ Inter Pro 1000 for Etherboot
+ Drivers are port from Intel's Linux driver e1000-3.1.23
+
+ ***************************************************************************/
+ /*****************************************************************************
+ *****************************************************************************
+
+ Copyright (c) 1999 - 2001, Intel Corporation
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the
documentation
+ and/or other materials provided with the distribution.
+
+ 3. Neither the name of Intel Corporation nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ *****************************************************************************
+
*****************************************************************************/
+
+ /*
+ * Copyright (C) Archway Digital Solutions.
+ *
+ * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina
dot org>
+ * 2/9/2002
+ */
+
+ /*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+ /* to get some global routines like printf */
+ #include "etherboot.h"
+ /* to get the interface to the body of the program */
+ #include "nic.h"
+ /* to get the PCI support functions, if this is a PCI NIC */
+ #include "pci.h"
+ /* to get our own prototype */
+ #include "cards.h"
+ #include "timer.h"
+
+ #undef virt_to_bus
+ #define virt_to_bus(x) ((unsigned long)x)
+
+ typedef unsigned char *dma_addr_t;
+ typedef unsigned char u8;
+ typedef signed char s8;
+ typedef unsigned short u16;
+ typedef signed short s16;
+ typedef unsigned int u32;
+ typedef signed int s32, atomic_t;
+
+ typedef unsigned long long u64;
+
+ /*
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the CRIS architecture, we just read/write the
+ * memory location directly.
+ */
+ #define readb(addr) (*(volatile unsigned char *) (addr))
+ #define readw(addr) (*(volatile unsigned short *) (addr))
+ #define readl(addr) (*(volatile unsigned int *) (addr))
+
+ #define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
+ #define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
+ #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
+
+ // jws - porting etherboot -> grub
+ #define udelay(n) waiton_timer2(((n)*TICKS_PER_MS)/1000)
+ #define mdelay(n) waiton_timer2(((n)*TICKS_PER_MS))
+
+ // #define DEBUG 1
+ #include "e1000.h"
+ #include "e1000_fxhw.h"
+ #include "e1000_phy.h"
+
+ struct pci_device *pci_dev;
+ u8 mac_addr[ETH_LENGTH_OF_ADDRESS];
+ unsigned int ioaddr;
+ u8 MacType;
+ u8 MediaType;
+ u8 ReportTxEarly;
+ u8 TbiCompatibilityEnable = TRUE;
+
+ u16 FlowControlHighWatermark = FC_DEFAULT_HI_THRESH;
+ u16 FlowControlLowWatermark = FC_DEFAULT_LO_THRESH;
+ u16 FlowControlPauseTime = FC_DEFAULT_TX_TIMER;
+ u8 FlowControlSendXon = TRUE;
+ u8 FlowControl = FLOW_CONTROL_NONE;
+ u8 OriginalFlowControl = FLOW_CONTROL_NONE;
+ u16 PciCommandWord;
+ u8 AutoNegFailed = 0;
+ u8 AutoNeg = 1;
+ u8 AutoNegAdvertised;
+ u32 PhyId;
+ u32 PhyAddress;
+ u8 WaitAutoNegComplete = 1;
+ u32 TxcwRegValue;
+ u8 GetLinkStatus = 1;
+ u8 TbiCompatibilityOn;
+ u8 AdapterStopped;
+
+ char tx_pool[128 + 16];
+ char rx_pool[128 + 16];
+ char packet[2096];
+
+ E1000_TRANSMIT_DESCRIPTOR *tx_base;
+ E1000_RECEIVE_DESCRIPTOR *rx_base;
+
+ int tx_head, tx_tail;
+ int rx_head, rx_tail, rx_last;
+
+ #include "e1000_phy.c"
+ #include "e1000_fxhw.c"
+
+
+ /*********************************************************************/
+ /*! @brief Reads the MAC address from the EEPROM
+ * @param Adapter board private structure
+ * @param NodeAddress pointer to an array of bytes
+ *********************************************************************/
+
+ static void
+ ReadNodeAddress (uint8_t * NodeAddress)
+ {
+ uint16_t EepromWordValue;
+ int i;
+
+ E1000_DBG ("ReadNodeAddress\n");
+
+ for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+ EepromWordValue = ReadEepromWord (EEPROM_NODE_ADDRESS_BYTE_0 +
(i / 2));
+ NodeAddress[i] = (uint8_t) (EepromWordValue & 0x00FF);
+ NodeAddress[i + 1] = (uint8_t) (EepromWordValue >> 8);
+ }
+
+ return;
+ }
+
+ void
+ fill_rx (void)
+ {
+ E1000_RECEIVE_DESCRIPTOR *rd;
+ rx_last = rx_tail;
+ rd = rx_base + rx_tail;
+ rx_tail = (rx_tail + 1) % 8;
+ memset (rd, 0, 16);
+ rd->BufferAddress.Lo32 = (u32) packet;
+ E1000_WRITE_REG (Rdt0, rx_tail);
+ }
+
+ void
+ init_descriptor (void)
+ {
+ u32 p;
+ u32 tctl, reg_tipg, tmp;
+ p = (u32) tx_pool;
+ if (p & 0xf)
+ p = (p + 0x10) & (~0xf);
+
+ tx_base = (PE1000_TRANSMIT_DESCRIPTOR) p;
+
+ E1000_WRITE_REG (Tdbal, (u32) tx_base);
+ E1000_WRITE_REG (Tdbah, 0);
+ E1000_WRITE_REG (Tdl, 128);
+ /* Setup the HW Tx Head and Tail descriptor pointers */
+
+ E1000_WRITE_REG (Tdh, 0);
+ E1000_WRITE_REG (Tdt, 0);
+ tx_tail = 0;
+
+ tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
+ (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
(E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
+ E1000_WRITE_REG (Tctl, tctl);
+
+ rx_tail = 0;
+ /* disable receive */
+ E1000_WRITE_REG (Rctl, 0);
+ p = (u32) rx_pool;
+ if (p & 0xf)
+ p = (p + 0x10) & (~0xf);
+ rx_base = (E1000_RECEIVE_DESCRIPTOR *) p;
+ E1000_WRITE_REG (Rdbal0, (u32) rx_base);
+ E1000_WRITE_REG (Rdbah0, 0);
+
+ E1000_WRITE_REG (Rdlen0, 128);
+ /* Setup the HW Rx Head and Tail Descriptor Pointers */
+ E1000_WRITE_REG (Rdh0, 0);
+ E1000_WRITE_REG (Rdt0, 0);
+
+ E1000_WRITE_REG (Rctl, E1000_RCTL_EN | E1000_RCTL_BAM |
E1000_RCTL_SZ_2048);
+ fill_rx ();
+ }
+
+ /* NIC specific static variables go here */
+
+ /**************************************************************************
+ RESET - Reset adapter
+ ***************************************************************************/
+ static void
+ e1000_reset (struct nic *nic)
+ {
+ /* put the card in its initial state */
+ E1000_WRITE_REG (Ctrl, E1000_CTRL_RST);
+ }
+
+ /**************************************************************************
+ POLL - Wait for a frame
+ ***************************************************************************/
+ static int
+ e1000_poll (struct nic *nic)
+ {
+ /* return true if there's an ethernet packet ready to read */
+ /* nic->packet should contain data on return */
+ /* nic->packetlen should contain length of data */
+ E1000_RECEIVE_DESCRIPTOR *rd;
+ rd = rx_base + rx_last;
+ if (!rd->ReceiveStatus & E1000_RXD_STAT_DD)
+ return 0;
+ // printf("recv: packet %! -> %! len=%d \n", packet+6,
packet,rd->Length);
+ memcpy (nic->packet, packet, rd->Length);
+ nic->packetlen = rd->Length;
+ fill_rx ();
+ return 1;
+ }
+
+ /**************************************************************************
+ TRANSMIT - Transmit a frame
+ ***************************************************************************/
+ static void
+ e1000_transmit (struct nic *nic, const char *d, /* Destination */
+ unsigned int t, /* Type */
+ unsigned int s, /* size */
+ const char *p)
+ { /* Packet */
+ /* send the packet to destination */
+ struct eth_hdr {
+ unsigned char dst_addr[ETH_ALEN];
+ unsigned char src_addr[ETH_ALEN];
+ unsigned short type;
+ } hdr;
+ unsigned char tx_buffer[1680];
+ unsigned short status;
+ int to;
+ int s1, s2;
+ int i;
+ PE1000_TRANSMIT_DESCRIPTOR txhd, txp;
+ DEBUGOUT("send\n");
+ memcpy (&hdr.dst_addr, d, ETH_ALEN);
+ memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
+
+ hdr.type = htons (t);
+ txhd = tx_base + tx_tail;
+ tx_tail = (tx_tail + 1) % 8;
+ txp = tx_base + tx_tail;
+ tx_tail = (tx_tail + 1) % 8;
+
+ txhd->BufferAddress.Lo32 = virt_to_bus (&hdr);
+ txhd->BufferAddress.Hi32 = 0;
+ txhd->Lower.DwordData = sizeof (hdr);
+ txhd->Upper.DwordData = 0;
+
+ txp->BufferAddress.Lo32 = virt_to_bus (p);
+ txp->BufferAddress.Hi32 = 0;
+ txp->Lower.DwordData = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
E1000_TXD_CMD_IFCS | s;
+ txp->Upper.DwordData = 0;
+
+ E1000_WRITE_REG (Tdt, tx_tail);
+ while (!(txp->Upper.DwordData & E1000_TXD_STAT_DD)) {
+ udelay (10); /* give the nic a chance to write to the
register */
+ }
+ DEBUGOUT("send end\n");
+ }
+
+ /**************************************************************************
+ DISABLE - Turn off ethernet interface
+ ***************************************************************************/
+ static void
+ e1000_disable (struct nic *nic)
+ {
+ E1000_WRITE_REG (Rctl, 0);
+ E1000_WRITE_REG (Tctl, 0);
+ mdelay (10);
+
+ }
+
+ /**************************************************************************
+ PROBE - Look for an adapter, this routine's visible to the outside
+ You should omit the last argument struct pci_device * for a non-PCI NIC
+ ***************************************************************************/
+ struct nic *
+ e1000_probe (struct nic *nic, unsigned short *probe_addrs, struct pci_device
*p)
+ {
+ unsigned short pci_command;
+ unsigned short new_command;
+ unsigned char pci_latency;
+ u32 dev_state;
+ u8 revision;
+ int i;
+
+ if (p == 0)
+ return 0;
+ pci_dev = p;
+ pcibios_read_config_dword(p->bus, p->devfn, PCI_BASE_ADDRESS_0,
&ioaddr);
+ ioaddr &= ~3; /* Mask the bit that says "this is an io addr" */
+ /* From Matt Hortman <address@hidden> */
+ /* MAC and Phy settings */
+
+ switch (p->dev_id) {
+ case PCI_DEVICE_ID_82542:
+ pcibios_read_config_byte (p->bus, p->devfn, PCI_REVISION,
&revision);
+ switch (revision) {
+ case WISEMAN_2_0_REV_ID:
+ MacType = MAC_WISEMAN_2_0;
+ break;
+ case WISEMAN_2_1_REV_ID:
+ MacType = MAC_WISEMAN_2_1;
+ break;
+ default:
+ MacType = MAC_WISEMAN_2_0;
+ E1000_ERR ("Could not identify 82542 revision\n");
+ }
+ break;
+ case PCI_DEVICE_ID_82543GC_FIBER:
+ case PCI_DEVICE_ID_82543GC_COPPER:
+ MacType = MAC_LIVENGOOD;
+ break;
+ case PCI_DEVICE_ID_82544EI_COPPER:
+ case PCI_DEVICE_ID_82544GC_CREB:
+ MacType = MAC_CORDOVA;
+ break;
+ default:
+ E1000_ERR ("Could not identify hardware\n");
+ return 0;
+ }
+ if (MacType != MACTYPE) {
+ printf("Please add -DMACTYPE=%d and rebuild the
driver\n",MacType);
+ return 0;
+ }
+
+ /* Identify the Hardware - this is done by the gigabit shared code
+ * in InitializeHardware, but it would help to identify the NIC
+ * before bringing the hardware online for use in CheckOptions. */
+
+ if ((E1000_REPORT_TX_EARLY == 0) || (E1000_REPORT_TX_EARLY == 1)) {
+ ReportTxEarly = E1000_REPORT_TX_EARLY;
+ } else {
+ #if MACTYPE < MAC_LIVENGOOD
+ ReportTxEarly = 0;
+ #else
+ ReportTxEarly = 1;
+ #endif
+ }
+ /* SoftwareInit() ends here */
+
+ /*
+ * check to make sure the bios properly set the
+ * 82557 (or 82558) to be bus master
+ *
+ * from eepro100.c in 2.2.9 kernel source
+ */
+
+ pcibios_read_config_word (p->bus, p->devfn, PCI_COMMAND,
&PciCommandWord);
+ new_command = PciCommandWord | PCI_COMMAND_MASTER | PCI_COMMAND_MEM;
+
+ if (PciCommandWord != new_command) {
+ printf ("\nThe PCI BIOS has not enabled this device!\n"
+ "Updating PCI command %hX->%hX. pci_bus %hhX
pci_device_fn %hhX\n",
+ PciCommandWord, new_command, p->bus, p->devfn);
+ pcibios_write_config_word (p->bus, p->devfn, PCI_COMMAND,
new_command);
+ PciCommandWord = new_command;
+ }
+ dev_state = E1000_READ_REG (Status);
+ #ifdef EEPROM_CHECKSUM
+ if (!ValidateEepromChecksum ()) {
+ printf ("The EEPROM Checksum Is Not Valid\n");
+ return 0;
+ }
+ #endif
+ ReadNodeAddress (mac_addr);
+ memcpy (nic->node_addr, mac_addr, ETH_ALEN);
+
+ printf("MAC address %!\n", mac_addr);
+
+ if (!InitializeHardware ()) {
+ E1000_ERR ("Hardware Initialization Failed\n");
+ return 0;
+ }
+
+ // CheckForLink ();
+ /* disable all the interrupt */
+ E1000_WRITE_REG (Imc, 0xffffffff);
+
+ init_descriptor ();
+ /* if board found */
+ {
+ /* point to NIC specific routines */
+ nic->reset = e1000_reset;
+ nic->poll = e1000_poll;
+ nic->transmit = e1000_transmit;
+ nic->disable = e1000_disable;
+ return nic;
+ }
+ /* else */
+ return 0;
+ }
diff -rc2P -x '*~' grub-0.93/netboot/e1000_fxhw.c
grub-0.93-e1000/netboot/e1000_fxhw.c
*** grub-0.93/netboot/e1000_fxhw.c 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000_fxhw.c 2003-03-14 12:21:42.000000000
+0000
***************
*** 0 ****
--- 1,987 ----
+ /*****************************************************************************
+ *****************************************************************************
+
+ Copyright (c) 1999 - 2001, Intel Corporation
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the
documentation
+ and/or other materials provided with the distribution.
+
+ 3. Neither the name of Intel Corporation nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ *****************************************************************************
+
*****************************************************************************/
+
+ /* Workfile: fxhw.c */
+ /* Revision: 42 */
+ /* Date: 8/03/01 10:39a */
+
+ #include "e1000.h"
+
+ #define IN
+ #define OUT
+
+ VOID AdapterStop(void);
+
+ BOOLEAN InitializeHardware(void);
+
+ VOID InitRxAddresses(void);
+
+ VOID
+ MulticastAddressListUpdate(PUCHAR MulticastAddressList,
+ UINT32 MulticastAddressCount, UINT32 Padding);
+
+ UINT32
+ HashMulticastAddress(PUCHAR MulticastAddress);
+
+ VOID MtaSet(UINT32 HashValue);
+
+ VOID
+ RarSet(PUCHAR MulticastAddress, UINT32 RarIndex);
+
+ VOID WriteVfta(UINT32 Offset, UINT32 Value);
+
+ VOID ClearVfta(void);
+
+ BOOLEAN SetupFlowControlAndLink(void);
+
+ BOOLEAN SetupPcsLink(UINT32 DeviceControlReg);
+
+ VOID ConfigFlowControlAfterLinkUp(void);
+
+ VOID ForceMacFlowControlSetting(void);
+
+ VOID CheckForLink(void);
+
+ VOID ClearHwStatsCounters(void);
+
+ VOID
+ GetSpeedAndDuplex(PUINT16 Speed, PUINT16 Duplex);
+
+ UINT16 ReadEepromWord(UINT16 Reg);
+
+ STATIC
+ VOID ShiftOutBits(UINT16 Data, UINT16 Count);
+
+ STATIC VOID RaiseClock(UINT32 * EecdRegValue);
+
+ STATIC VOID LowerClock(UINT32 * EecdRegValue);
+
+ STATIC USHORT ShiftInBits(void);
+
+ STATIC VOID EepromCleanup(void);
+
+ BOOLEAN ValidateEepromChecksum(void);
+
+ VOID UpdateEepromChecksum(void);
+
+ BOOLEAN WriteEepromWord(USHORT reg, USHORT data);
+
+ STATIC UINT16 WaitEepromCommandDone(void);
+
+ STATIC VOID StandBy(void);
+
+ UINT32 ReadPartNumber(void);
+
+ VOID IdLedOn(void);
+
+ VOID IdLedOff(void);
+
+ VOID SetIdLedForPCIX(void);
+
+ BOOLEAN IsLowProfile(void);
+ #if 1
+ VOID AdapterStop(void)
+ {
+
+ UINT32 IcrContents;
+
+ UINT16 tPciCommandWord;
+
+ DEBUGFUNC("AdapterStop")
+
+ if (AdapterStopped) {
+ DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
+ return;
+ }
+
+ AdapterStopped = TRUE;
+
+ if (MacType == MAC_WISEMAN_2_0) {
+ if (PciCommandWord & CMD_MEM_WRT_INVALIDATE) {
+ DEBUGOUT("Disabling MWI on rev 2.0 Wiseman silicon\n");
+
+ tPciCommandWord =
+ PciCommandWord & ~CMD_MEM_WRT_INVALIDATE;
+
+ WritePciConfigWord(PCI_COMMAND_REGISTER, &tPciCommandWord);
+ }
+ }
+
+ DEBUGOUT("Masking off all interrupts\n");
+ E1000_WRITE_REG(Imc, 0xffffffff);
+
+ E1000_WRITE_REG(Rctl, 0);
+ E1000_WRITE_REG(Tctl, 0);
+
+ TbiCompatibilityOn = FALSE;
+
+ DelayInMilliseconds(10);
+
+ DEBUGOUT("Issuing a global reset to MAC\n");
+ E1000_WRITE_REG(Ctrl, E1000_CTRL_RST);
+
+ DelayInMilliseconds(10);
+
+ DEBUGOUT("Masking off all interrupts\n");
+ E1000_WRITE_REG(Imc, 0xffffffff);
+
+ IcrContents = E1000_READ_REG(Icr);
+
+ if (MacType == MAC_WISEMAN_2_0) {
+ if (PciCommandWord & CMD_MEM_WRT_INVALIDATE) {
+ WritePciConfigWord(PCI_COMMAND_REGISTER,
+ &PciCommandWord);
+ }
+ }
+
+ }
+ #endif
+
+ BOOLEAN InitializeHardware(void)
+ {
+ UINT i;
+ UINT16 tPciCommandWord;
+ BOOLEAN Status;
+ UINT32 RegisterValue;
+
+ DEBUGFUNC("InitializeHardware");
+
+ #if MACTYPE != MAC_LIVENGOOD
+ TbiCompatibilityEnable = FALSE;
+ #endif
+
+ #if (MACTYPE >= MAC_LIVENGOOD)
+ RegisterValue = E1000_READ_REG(Status);
+ if (RegisterValue & E1000_STATUS_TBIMODE) {
+ MediaType = MEDIA_TYPE_FIBER;
+
+ TbiCompatibilityEnable = FALSE;
+ } else {
+ MediaType = MEDIA_TYPE_COPPER;
+ }
+ #else
+
+ MediaType = MEDIA_TYPE_FIBER;
+ #endif
+
+ DEBUGOUT("Initializing the IEEE VLAN\n");
+ E1000_WRITE_REG(Vet, 0);
+
+ ClearVfta();
+
+ #if MACTYPE == MAC_WISEMAN_2_0
+
+ if (PciCommandWord & CMD_MEM_WRT_INVALIDATE) {
+ DEBUGOUT("Disabling MWI on rev 2.0 Wiseman silicon\n");
+
+ tPciCommandWord =
+ PciCommandWord & ~CMD_MEM_WRT_INVALIDATE;
+
+ WritePciConfigWord(PCI_COMMAND_REGISTER, &tPciCommandWord);
+ }
+
+ E1000_WRITE_REG(Rctl, E1000_RCTL_RST);
+
+ DelayInMilliseconds(5);
+ #endif
+
+ InitRxAddresses();
+
+ #if MACTYPE == MAC_WISEMAN_2_0
+ E1000_WRITE_REG(Rctl, 0);
+
+ DelayInMilliseconds(1);
+
+ if (PciCommandWord & CMD_MEM_WRT_INVALIDATE) {
+ WritePciConfigWord(PCI_COMMAND_REGISTER,
+ &PciCommandWord);
+ }
+
+ #endif
+
+ DEBUGOUT("Zeroing the MTA\n");
+ for (i = 0; i < E1000_MC_TBL_SIZE; i++) {
+ E1000_WRITE_REG(Mta[i], 0);
+ }
+
+ Status = SetupFlowControlAndLink();
+
+
+ return (Status);
+ }
+
+ VOID InitRxAddresses(void)
+ {
+ UINT i;
+ UINT32 HwLowAddress;
+ UINT32 HwHighAddress;
+
+ DEBUGFUNC("InitRxAddresses")
+
+ DEBUGOUT("Programming IA into RAR[0]\n");
+ HwLowAddress = (mac_addr[0] |
+ (mac_addr[1] << 8) |
+ (mac_addr[2] << 16) |
+ (mac_addr[3] << 24));
+
+ HwHighAddress = (mac_addr[4] |
+ (mac_addr[5] << 8) | E1000_RAH_AV);
+
+ E1000_WRITE_REG(Rar[0].Low, HwLowAddress);
+ E1000_WRITE_REG(Rar[0].High, HwHighAddress);
+
+ DEBUGOUT("Clearing RAR[1-15]\n");
+ for (i = 1; i < E1000_RAR_ENTRIES; i++) {
+ E1000_WRITE_REG(Rar[i].Low, 0);
+ E1000_WRITE_REG(Rar[i].High, 0);
+ }
+
+ return;
+ }
+
+ VOID ClearVfta(void)
+ {
+ UINT32 Offset;
+
+ for (Offset = 0; Offset < E1000_VLAN_FILTER_TBL_SIZE; Offset++)
+ E1000_WRITE_REG(Vfta[Offset], 0);
+
+ }
+
+ BOOLEAN SetupFlowControlAndLink(void)
+ {
+ UINT32 TempEepromWord;
+ UINT32 DeviceControlReg;
+ UINT32 ExtDevControlReg;
+ BOOLEAN Status = TRUE;
+
+ DEBUGFUNC("SetupFlowControlAndLink")
+
+ TempEepromWord = ReadEepromWord(EEPROM_INIT_CONTROL1_REG);
+
+ DeviceControlReg =
+ (((TempEepromWord & EEPROM_WORD0A_SWDPIO) << SWDPIO_SHIFT) |
+ ((TempEepromWord & EEPROM_WORD0A_ILOS) << ILOS_SHIFT));
+ #ifndef USE_COMPLEX_VERSION
+ Status = PhySetup(DeviceControlReg);
+ E1000_WRITE_REG(Fcrtl, 0);
+ E1000_WRITE_REG(Fcrth, 0);
+ #else
+ // if (Adapter->DmaFairness)
+ // DeviceControlReg |= E1000_CTRL_PRIOR;
+ TempEepromWord = ReadEepromWord(EEPROM_INIT_CONTROL2_REG);
+
+ if (FlowControl > FLOW_CONTROL_FULL) {
+ if ((TempEepromWord & EEPROM_WORD0F_PAUSE_MASK) == 0)
+ FlowControl = FLOW_CONTROL_NONE;
+ else if ((TempEepromWord & EEPROM_WORD0F_PAUSE_MASK) ==
+ EEPROM_WORD0F_ASM_DIR) FlowControl =
+ FLOW_CONTROL_TRANSMIT_PAUSE;
+ else
+ FlowControl = FLOW_CONTROL_FULL;
+ }
+ OriginalFlowControl = FlowControl;
+
+ #if MACTTYPE == MAC_WISEMAN_2_0
+ FlowControl &= (~FLOW_CONTROL_TRANSMIT_PAUSE);
+ #endif
+
+ #if ((MACTYPE < MAC_LIVENGOOD))
+ if (ReportTxEarly == 1) FlowControl &= (~FLOW_CONTROL_RECEIVE_PAUSE);
+ // DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
+ // FlowControl);
+ #endif
+
+ #if (MACTYPE >= MAC_LIVENGOOD)
+ ExtDevControlReg = ((TempEepromWord & EEPROM_WORD0F_SWPDIO_EXT)
+ << SWDPIO__EXT_SHIFT);
+ E1000_WRITE_REG(Exct, ExtDevControlReg);
+ #endif
+
+ #if (MACTYPE >= MAC_LIVENGOOD)
+ # ifdef USE_FIBER
+ Status = SetupPcsLink(DeviceControlReg);
+ # else
+ Status = PhySetup(DeviceControlReg);
+ # endif
+ #else
+ Status = SetupPcsLink(DeviceControlReg);
+ #endif
+
+
+ DEBUGOUT
+ ("Initializing the Flow Control address, type and timer regs\n");
+
+ E1000_WRITE_REG(Fcal, FLOW_CONTROL_ADDRESS_LOW);
+ E1000_WRITE_REG(Fcah, FLOW_CONTROL_ADDRESS_HIGH);
+ E1000_WRITE_REG(Fct, FLOW_CONTROL_TYPE);
+ E1000_WRITE_REG(Fcttv, FlowControlPauseTime);
+
+ if (!(FlowControl & FLOW_CONTROL_TRANSMIT_PAUSE)) {
+ E1000_WRITE_REG(Fcrtl, 0);
+ E1000_WRITE_REG(Fcrth, 0);
+ } else {
+
+ if (FlowControlSendXon) {
+ E1000_WRITE_REG(Fcrtl,
+ ( FlowControlLowWatermark | E1000_FCRTL_XONE));
+ E1000_WRITE_REG(Fcrth, FlowControlHighWatermark);
+ } else {
+ E1000_WRITE_REG(Fcrtl, FlowControlLowWatermark);
+ E1000_WRITE_REG(Fcrth, FlowControlHighWatermark);
+ }
+ }
+
+ #endif
+ return (Status);
+ }
+
+ #ifdef USE_FIBER
+ BOOLEAN SetupPcsLink(UINT32 DeviceControlReg)
+ {
+ UINT32 i;
+ UINT32 StatusContents;
+ UINT32 TctlReg;
+ UINT32 TransmitConfigWord=0;
+ UINT32 Shift32;
+
+ DEBUGFUNC("SetupPcsLink")
+
+ TctlReg = E1000_READ_REG(Tctl);
+ Shift32 = E1000_FDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ E1000_WRITE_REG(Tctl, TctlReg);
+
+ switch (FlowControl) {
+ case FLOW_CONTROL_NONE:
+
+ TransmitConfigWord = (E1000_TXCW_ANE | E1000_TXCW_FD);
+
+ break;
+
+ case FLOW_CONTROL_RECEIVE_PAUSE:
+
+ TransmitConfigWord =
+ (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+
+ break;
+
+ case FLOW_CONTROL_TRANSMIT_PAUSE:
+
+ TransmitConfigWord =
+ (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
+
+ break;
+
+ case FLOW_CONTROL_FULL:
+
+ TransmitConfigWord =
+ (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+
+ break;
+
+ default:
+
+ DEBUGOUT("Flow control param set incorrectly\n");
+ ASSERT(0);
+ break;
+ }
+
+ DEBUGOUT("Auto-negotiation enabled\n");
+
+ E1000_WRITE_REG(Txcw, TransmitConfigWord);
+ E1000_WRITE_REG(Ctrl, DeviceControlReg);
+
+ TxcwRegValue = TransmitConfigWord;
+ DelayInMilliseconds(1);
+
+ if (!(E1000_READ_REG(Ctrl) & E1000_CTRL_SWDPIN1)) {
+
+ DEBUGOUT("Looking for Link\n");
+ for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+ DelayInMilliseconds(10);
+
+ StatusContents = E1000_READ_REG(Status);
+ if (StatusContents & E1000_STATUS_LU)
+ break;
+ }
+
+ if (i == (LINK_UP_TIMEOUT / 10)) {
+
+ DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+
+ AutoNegFailed = 1;
+ CheckForLink();
+ AutoNegFailed = 0;
+ } else {
+ AutoNegFailed = 0;
+ DEBUGOUT("Valid Link Found\n");
+ }
+ } else {
+ DEBUGOUT("No Signal Detected\n");
+ }
+
+ return (TRUE);
+ }
+ #endif
+
+
+ #ifdef USE_COMPLEX_VERSION
+ VOID ConfigFlowControlAfterLinkUp(void)
+ {
+ UINT16 MiiStatusReg, MiiNWayAdvertiseReg, MiiNWayBasePgAbleReg;
+ UINT16 Speed, Duplex;
+
+ DEBUGFUNC("ConfigFlowControlAfterLinkUp")
+
+ if (
+ ((MediaType == MEDIA_TYPE_FIBER)
+ && (AutoNegFailed))
+ || ((MediaType == MEDIA_TYPE_COPPER)
+ && (!AutoNeg))) {
+ ForceMacFlowControlSetting();
+ }
+
+ if ((MediaType == MEDIA_TYPE_COPPER) && AutoNeg) {
+
+ MiiStatusReg = ReadPhyRegister(
+ PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ MiiStatusReg = ReadPhyRegister(
+ PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ if (MiiStatusReg & MII_SR_AUTONEG_COMPLETE) {
+
+ MiiNWayAdvertiseReg = ReadPhyRegister(
+ PHY_AUTONEG_ADVERTISEMENT,
+ PhyAddress);
+
+ MiiNWayBasePgAbleReg = ReadPhyRegister(
+ PHY_AUTONEG_LP_BPA,
+ PhyAddress);
+
+ if ((MiiNWayAdvertiseReg & NWAY_AR_PAUSE) &&
+ (MiiNWayBasePgAbleReg & NWAY_LPAR_PAUSE)) {
+
+ if (OriginalFlowControl == FLOW_CONTROL_FULL) {
+ FlowControl = FLOW_CONTROL_FULL;
+ DEBUGOUT("Flow Control = FULL.\r\n");
+ } else {
+ FlowControl = FLOW_CONTROL_RECEIVE_PAUSE;
+ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
+ }
+ }
+
+ else if (!(MiiNWayAdvertiseReg & NWAY_AR_PAUSE) &&
+ (MiiNWayAdvertiseReg & NWAY_AR_ASM_DIR) &&
+ (MiiNWayBasePgAbleReg & NWAY_LPAR_PAUSE) &&
+ (MiiNWayBasePgAbleReg & NWAY_LPAR_ASM_DIR)) {
+ FlowControl = FLOW_CONTROL_TRANSMIT_PAUSE;
+ DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
+ }
+
+ else if ((MiiNWayAdvertiseReg & NWAY_AR_PAUSE) &&
+ (MiiNWayAdvertiseReg & NWAY_AR_ASM_DIR) &&
+ !(MiiNWayBasePgAbleReg & NWAY_LPAR_PAUSE) &&
+ (MiiNWayBasePgAbleReg & NWAY_LPAR_ASM_DIR)) {
+ FlowControl = FLOW_CONTROL_RECEIVE_PAUSE;
+ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
+ }
+
+ else if (OriginalFlowControl == FLOW_CONTROL_NONE ||
+ OriginalFlowControl ==
+ FLOW_CONTROL_TRANSMIT_PAUSE) {
+ FlowControl = FLOW_CONTROL_NONE;
+ DEBUGOUT("Flow Control = NONE.\r\n");
+ } else {
+ FlowControl = FLOW_CONTROL_RECEIVE_PAUSE;
+ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
+ }
+
+ GetSpeedAndDuplex(&Speed, &Duplex);
+
+ if (Duplex == HALF_DUPLEX)
+ FlowControl = FLOW_CONTROL_NONE;
+
+ ForceMacFlowControlSetting();
+ } else {
+ DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
+ }
+ }
+ }
+
+ VOID ForceMacFlowControlSetting(void)
+ {
+ UINT32 CtrlRegValue;
+
+ DEBUGFUNC("ForceMacFlowControlSetting")
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+
+ switch (FlowControl) {
+ case FLOW_CONTROL_NONE:
+
+ CtrlRegValue &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
+ break;
+
+ case FLOW_CONTROL_RECEIVE_PAUSE:
+
+ CtrlRegValue &= (~E1000_CTRL_TFCE);
+ CtrlRegValue |= E1000_CTRL_RFCE;
+ break;
+
+ case FLOW_CONTROL_TRANSMIT_PAUSE:
+
+ CtrlRegValue &= (~E1000_CTRL_RFCE);
+ CtrlRegValue |= E1000_CTRL_TFCE;
+ break;
+
+ case FLOW_CONTROL_FULL:
+
+ CtrlRegValue |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
+ break;
+
+ default:
+
+ DEBUGOUT("Flow control param set incorrectly\n");
+ ASSERT(0);
+
+ break;
+ }
+
+ #if (MACTYPE == MAC_WISEMAN_2_0)
+ CtrlRegValue &= (~E1000_CTRL_TFCE);
+ #endif
+ E1000_WRITE_REG(Ctrl, CtrlRegValue);
+ }
+
+ VOID CheckForLink(void)
+ {
+ UINT32 RxcwRegValue;
+ UINT32 CtrlRegValue;
+ UINT32 StatusRegValue;
+ UINT32 RctlRegValue;
+ UINT16 PhyData;
+ UINT16 LinkPartnerCapability;
+
+ DEBUGFUNC("CheckForLink")
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+
+ StatusRegValue = E1000_READ_REG(Status);
+
+ RxcwRegValue = E1000_READ_REG(Rxcw);
+
+ if (MediaType == MEDIA_TYPE_COPPER && GetLinkStatus) {
+
+ PhyData = ReadPhyRegister(
+ PHY_MII_STATUS_REG, PhyAddress);
+
+ PhyData = ReadPhyRegister(
+ PHY_MII_STATUS_REG, PhyAddress);
+
+ if (PhyData & MII_SR_LINK_STATUS) {
+ GetLinkStatus = FALSE;
+ } else {
+ DEBUGOUT("**** CFL - No link detected. ****\r\n");
+ return;
+ }
+
+ if (!AutoNeg) {
+ return;
+ }
+
+ switch (PhyId) {
+ case PAXSON_PHY_88E1000:
+ case PAXSON_PHY_88E1000S:
+ case PAXSON_PHY_INTEGRATED:
+
+ #if (MACTYPE > MAC_WAINWRIGHT)
+ DEBUGOUT
+ ("CFL - Auto-Neg complete. Configuring Collision
Distance.");
+ ConfigureCollisionDistance();
+ #else
+
+ PhyData = ReadPhyRegister(
+ PXN_PHY_SPEC_STAT_REG,
+ PhyAddress);
+
+ DEBUGOUT1("CFL - Auto-Neg complete. PhyData = %x\r\n",
+ PhyData);
+ ConfigureMacToPhySettings( PhyData);
+ #endif
+
+ ConfigFlowControlAfterLinkUp();
+ break;
+
+ default:
+ DEBUGOUT("CFL - Invalid PHY detected.\r\n");
+
+ }
+
+ if (TbiCompatibilityEnable) {
+ LinkPartnerCapability = ReadPhyRegister(
+ PHY_AUTONEG_LP_BPA,
+ PhyAddress);
+ if (LinkPartnerCapability & (NWAY_LPAR_10T_HD_CAPS |
+ NWAY_LPAR_10T_FD_CAPS |
+ NWAY_LPAR_100TX_HD_CAPS |
+ NWAY_LPAR_100TX_FD_CAPS |
+ NWAY_LPAR_100T4_CAPS)) {
+
+ if (TbiCompatibilityOn) {
+
+ RctlRegValue = E1000_READ_REG(Rctl);
+ RctlRegValue &= ~E1000_RCTL_SBP;
+ E1000_WRITE_REG(Rctl, RctlRegValue);
+ TbiCompatibilityOn = FALSE;
+ }
+ } else {
+
+ if (!TbiCompatibilityOn) {
+ TbiCompatibilityOn = TRUE;
+ RctlRegValue = E1000_READ_REG(Rctl);
+ RctlRegValue |= E1000_RCTL_SBP;
+ E1000_WRITE_REG(Rctl, RctlRegValue);
+ }
+ }
+ }
+ }
+
+ else
+ if ((MediaType == MEDIA_TYPE_FIBER) &&
+ (!(StatusRegValue & E1000_STATUS_LU)) &&
+ (!(CtrlRegValue & E1000_CTRL_SWDPIN1)) &&
+ (!(RxcwRegValue & E1000_RXCW_C))) {
+ if (AutoNegFailed == 0) {
+ AutoNegFailed = 1;
+ return;
+ }
+
+ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
+
+ E1000_WRITE_REG(Txcw, (TxcwRegValue & ~E1000_TXCW_ANE));
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+ CtrlRegValue |= (E1000_CTRL_SLU | E1000_CTRL_FD);
+ E1000_WRITE_REG(Ctrl, CtrlRegValue);
+
+ ConfigFlowControlAfterLinkUp();
+ }
+ else if ((MediaType == MEDIA_TYPE_FIBER) &&
+ (CtrlRegValue & E1000_CTRL_SLU) &&
+ (RxcwRegValue & E1000_RXCW_C)) {
+
+ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
+
+ E1000_WRITE_REG(Txcw, TxcwRegValue);
+
+ E1000_WRITE_REG(Ctrl, (CtrlRegValue & ~E1000_CTRL_SLU));
+ }
+
+ return;
+ }
+
+
+ VOID
+ GetSpeedAndDuplex(PUINT16 Speed, PUINT16 Duplex)
+ {
+ UINT32 DeviceStatusReg;
+
+ DEBUGFUNC("GetSpeedAndDuplex")
+
+ // if (AdapterStopped) {
+ // *Speed = 0;
+ // *Duplex = 0;
+ // return;
+ // }
+
+ # if (MACTYPE >= MAC_LIVENGOOD)
+ DEBUGOUT("Livengood MAC\n");
+ DeviceStatusReg = E1000_READ_REG(Status);
+ if (DeviceStatusReg & E1000_STATUS_SPEED_1000) {
+ *Speed = SPEED_1000;
+ DEBUGOUT(" 1000 Mbs\n");
+ } else if (DeviceStatusReg & E1000_STATUS_SPEED_100) {
+ *Speed = SPEED_100;
+ DEBUGOUT(" 100 Mbs\n");
+ } else {
+ *Speed = SPEED_10;
+ DEBUGOUT(" 10 Mbs\n");
+ }
+
+ if (DeviceStatusReg & E1000_STATUS_FD) {
+ *Duplex = FULL_DUPLEX;
+ DEBUGOUT(" Full Duplex\r\n");
+ } else {
+ *Duplex = HALF_DUPLEX;
+ DEBUGOUT(" Half Duplex\r\n");
+ }
+ #else
+ DEBUGOUT("Wiseman MAC - 1000 Mbs, Full Duplex\r\n");
+ *Speed = SPEED_1000;
+ *Duplex = FULL_DUPLEX;
+ #endif
+
+ return;
+ }
+ #endif
+
+ UINT16 ReadEepromWord(UINT16 Reg)
+ {
+ UINT16 Data;
+
+ ASSERT(Reg < EEPROM_WORD_SIZE);
+
+ E1000_WRITE_REG(Eecd, E1000_EECS);
+
+ ShiftOutBits(EEPROM_READ_OPCODE, 3);
+ ShiftOutBits(Reg, 6);
+
+ Data = ShiftInBits();
+
+ EepromCleanup();
+ return (Data);
+ }
+
+ STATIC
+ VOID ShiftOutBits(UINT16 Data, UINT16 Count)
+ {
+ UINT32 EecdRegValue;
+ UINT32 Mask;
+
+ Mask = 0x01 << (Count - 1);
+
+ EecdRegValue = E1000_READ_REG(Eecd);
+
+ EecdRegValue &= ~(E1000_EEDO | E1000_EEDI);
+
+ do {
+
+ EecdRegValue &= ~E1000_EEDI;
+
+ if (Data & Mask)
+ EecdRegValue |= E1000_EEDI;
+
+ E1000_WRITE_REG(Eecd, EecdRegValue);
+
+ DelayInMicroseconds(50);
+
+ RaiseClock(&EecdRegValue);
+ LowerClock(&EecdRegValue);
+
+ Mask = Mask >> 1;
+
+ } while (Mask);
+
+ EecdRegValue &= ~E1000_EEDI;
+
+ E1000_WRITE_REG(Eecd, EecdRegValue);
+ }
+
+ STATIC VOID RaiseClock(UINT32 * EecdRegValue)
+ {
+
+ *EecdRegValue = *EecdRegValue | E1000_EESK;
+
+ E1000_WRITE_REG(Eecd, *EecdRegValue);
+
+ DelayInMicroseconds(50);
+ }
+
+ STATIC VOID LowerClock(UINT32 * EecdRegValue)
+ {
+
+ *EecdRegValue = *EecdRegValue & ~E1000_EESK;
+
+ E1000_WRITE_REG(Eecd, *EecdRegValue);
+
+ DelayInMicroseconds(50);
+ }
+
+ STATIC UINT16 ShiftInBits(void)
+ {
+ UINT32 EecdRegValue;
+ UINT i;
+ UINT16 Data;
+
+ EecdRegValue = E1000_READ_REG(Eecd);
+
+ EecdRegValue &= ~(E1000_EEDO | E1000_EEDI);
+ Data = 0;
+
+ for (i = 0; i < 16; i++) {
+ Data = Data << 1;
+ RaiseClock(&EecdRegValue);
+
+ EecdRegValue = E1000_READ_REG(Eecd);
+
+ EecdRegValue &= ~(E1000_EEDI);
+ if (EecdRegValue & E1000_EEDO)
+ Data |= 1;
+
+ LowerClock(&EecdRegValue);
+ }
+
+ return (Data);
+ }
+
+ STATIC VOID EepromCleanup()
+ {
+ UINT32 EecdRegValue;
+
+ EecdRegValue = E1000_READ_REG(Eecd);
+
+ EecdRegValue &= ~(E1000_EECS | E1000_EEDI);
+
+ E1000_WRITE_REG(Eecd, EecdRegValue);
+
+ RaiseClock(&EecdRegValue);
+ LowerClock(&EecdRegValue);
+ }
+ #ifdef EEPROM_CHECKSUM
+ BOOLEAN ValidateEepromChecksum(void)
+ {
+ UINT16 Checksum = 0;
+ UINT16 Iteration;
+
+ for (Iteration = 0; Iteration < (EEPROM_CHECKSUM_REG + 1); Iteration++)
+ Checksum += ReadEepromWord(Iteration);
+
+ if (Checksum == (UINT16) EEPROM_SUM)
+ return (TRUE);
+ else
+ return (FALSE);
+ }
+
+ VOID UpdateEepromChecksum(void)
+ {
+ UINT16 Checksum = 0;
+ UINT16 Iteration;
+
+ for (Iteration = 0; Iteration < EEPROM_CHECKSUM_REG; Iteration++)
+ Checksum += ReadEepromWord(Iteration);
+
+ Checksum = (UINT16) EEPROM_SUM - Checksum;
+
+ WriteEepromWord(EEPROM_CHECKSUM_REG, Checksum);
+ }
+
+ BOOLEAN WriteEepromWord(UINT16 Reg, UINT16 Data)
+ {
+
+ E1000_WRITE_REG(Eecd, E1000_EECS);
+
+ StandBy();
+
+ ShiftOutBits(EEPROM_EWEN_OPCODE, 5);
+ ShiftOutBits(Reg, 4);
+
+ StandBy();
+
+ ShiftOutBits(EEPROM_ERASE_OPCODE, 3);
+ ShiftOutBits(Reg, 6);
+
+ if (!WaitEepromCommandDone()) {
+ return (FALSE);
+ }
+
+ ShiftOutBits(EEPROM_EWDS_OPCODE, 5);
+ ShiftOutBits(Reg, 4);
+
+ StandBy();
+
+ ShiftOutBits(EEPROM_EWEN_OPCODE, 5);
+ ShiftOutBits(Reg, 4);
+
+ StandBy();
+
+ ShiftOutBits(EEPROM_WRITE_OPCODE, 3);
+ ShiftOutBits(Reg, 6);
+ ShiftOutBits(Data, 16);
+
+ if (!WaitEepromCommandDone()) {
+ return (FALSE);
+ }
+
+ ShiftOutBits(EEPROM_EWDS_OPCODE, 5);
+ ShiftOutBits(Reg, 4);
+
+ EepromCleanup();
+
+ return (TRUE);
+ }
+
+ STATIC UINT16 WaitEepromCommandDone(void)
+ {
+ UINT32 EecdRegValue;
+ UINT i;
+
+ StandBy();
+
+ for (i = 0; i < 200; i++) {
+ EecdRegValue = E1000_READ_REG(Eecd);
+
+ if (EecdRegValue & E1000_EEDO)
+ return (TRUE);
+
+ DelayInMicroseconds(5);
+ }
+
+ return (FALSE);
+ }
+
+ STATIC VOID StandBy(void)
+ {
+ UINT32 EecdRegValue;
+
+ EecdRegValue = E1000_READ_REG(Eecd);
+
+ EecdRegValue &= ~(E1000_EECS | E1000_EESK);
+
+ E1000_WRITE_REG(Eecd, EecdRegValue);
+
+ DelayInMicroseconds(5);
+
+ EecdRegValue |= E1000_EECS;
+
+ E1000_WRITE_REG(Eecd, EecdRegValue);
+ }
+ #endif
+
+
diff -rc2P -x '*~' grub-0.93/netboot/e1000_fxhw.h
grub-0.93-e1000/netboot/e1000_fxhw.h
*** grub-0.93/netboot/e1000_fxhw.h 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000_fxhw.h 2003-03-14 12:21:42.000000000
+0000
***************
*** 0 ****
--- 1,1329 ----
+ /*****************************************************************************
+ *****************************************************************************
+
+ Copyright (c) 1999 - 2001, Intel Corporation
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the
documentation
+ and/or other materials provided with the distribution.
+
+ 3. Neither the name of Intel Corporation nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ *****************************************************************************
+
*****************************************************************************/
+
+ /* Workfile: fxhw.h */
+ /* Revision: 37 */
+ /* Date: 7/19/01 5:12p */
+
+ #ifndef _FXHW_
+ #define _FXHW_
+ #include "e1000.h"
+
+ #define _FXHW_
+
+ #define ASSERT(x) if(!(x)) printf("E1000: Asser Fail")
+ #define DelayInMicroseconds(x) udelay(x)
+ #define DelayInMilliseconds(x) mdelay(x)
+
+ typedef uint8_t UCHAR, UINT8, BOOLEAN, *PUCHAR, *PUINT8;
+ typedef uint16_t USHORT, UINT16, *PUSHORT, *PUINT16;
+ typedef uint32_t UINT, ULONG, UINT32, *PUINT, *PULONG, *PUINT32;
+ typedef void VOID, *PVOID;
+ typedef struct _E1000_64_BIT_PHYSICAL_ADDRESS {
+ UINT32 Lo32;
+ UINT32 Hi32;
+ } E1000_64_BIT_PHYSICAL_ADDRESS, *PE1000_64_BIT_PHYSICAL_ADDRESS;
+
+ #define IN
+ #define OUT
+ #define STATIC static
+
+ #define MSGOUT(S, A, B) printk(S "\n", A, B)
+ #ifdef DEBUG
+ #define DEBUGFUNC(F) DEBUGOUT(F);
+ #define DEBUGOUT(S) printf(S)
+ #define DEBUGOUT1(S,A) printf(S,A)
+ #define DEBUGOUT2(S,A,B) printf(S,A,B)
+ #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
+ #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
+
+ #else
+ #define DEBUGFUNC(F)
+ #define DEBUGOUT(S)
+ #define DEBUGOUT1(S,A)
+ #define DEBUGOUT2(S,A,B)
+ #define DEBUGOUT3(S,A,B,C)
+ #define DEBUGOUT7(S,A,B,C,D,E,F,G)
+ #endif
+
+ #define WritePciConfigWord(Reg, PValue)
pcibios_write_config_word(pci_dev->bus,pci_dev->devfn, Reg, *PValue)
+
+ #define MAC_DECODE_SIZE (128 * 1024)
+ /*
+ * We are going to using them for pre process to cut down code size
+ * default build for MAC_LIVENGOOD
+ *
+ typedef enum _MAC_TYPE {
+ MAC_WISEMAN_2_0 = 0,
+ MAC_WISEMAN_2_1,
+ MAC_LIVENGOOD,
+ MAC_WAINWRIGHT,
+ MAC_CORDOVA,
+ NUM_MACS
+ } MAC_TYPE, *PMAC_TYPE;
+ */
+
+ #define MAC_WISEMAN_2_0 0
+ #define MAC_WISEMAN_2_1 1
+ #define MAC_LIVENGOOD 2
+ #define MAC_WAINWRIGHT 3
+ #define MAC_CORDOVA 4
+ #define NUM_MACS 5
+
+ #ifndef MACTYPE
+ #define MACTYPE MAC_LIVENGOOD
+ #endif
+
+ #define WISEMAN_2_0_REV_ID 2
+ #define WISEMAN_2_1_REV_ID 3
+
+ typedef enum _GIGABIT_MEDIA_TYPE {
+ MEDIA_TYPE_COPPER = 0,
+ MEDIA_TYPE_FIBER = 1,
+ NUM_MEDIA_TYPES
+ } GIGABIT_MEDIA_TYPE, *PGIGABIT_MEDIA_TYPE;
+
+ typedef enum _SPEED_DUPLEX_TYPE {
+ HALF_10 = 0,
+ FULL_10 = 1,
+ HALF_100 = 2,
+ FULL_100 = 3
+ } SPEED_DUPLEX_TYPE, *PSPEED_DUPLEX_TYPE;
+
+ #define SPEED_10 10
+ #define SPEED_100 100
+ #define SPEED_1000 1000
+ #define HALF_DUPLEX 1
+ #define FULL_DUPLEX 2
+
+ #define ENET_HEADER_SIZE 14
+ #define MAXIMUM_ETHERNET_PACKET_SIZE 1514
+ #define MINIMUM_ETHERNET_PACKET_SIZE 60
+ #define CRC_LENGTH 4
+
+ #define MAX_JUMBO_FRAME_SIZE (0x3F00)
+
+ #define ISL_CRC_LENGTH 4
+
+ #define MAXIMUM_VLAN_ETHERNET_PACKET_SIZE 1514
+ #define MINIMUM_VLAN_ETHERNET_PACKET_SIZE 60
+ #define VLAN_TAG_SIZE 4
+
+ #define ETHERNET_IEEE_VLAN_TYPE 0x8100
+ #define ETHERNET_IP_TYPE 0x0800
+ #define ETHERNET_IPX_TYPE 0x8037
+ #define ETHERNET_IPX_OLD_TYPE 0x8137
+ #define MAX_802_3_LEN_FIELD 0x05DC
+
+ #define ETHERNET_ARP_TYPE 0x0806
+ #define ETHERNET_XNS_TYPE 0x0600
+ #define ETHERNET_X25_TYPE 0x0805
+ #define ETHERNET_BANYAN_TYPE 0x0BAD
+ #define ETHERNET_DECNET_TYPE 0x6003
+ #define ETHERNET_APPLETALK_TYPE 0x809B
+ #define ETHERNET_SNA_TYPE 0x80D5
+ #define ETHERNET_SNMP_TYPE 0x814C
+
+ #define IP_OFF_MF_BIT 0x0002
+ #define IP_OFF_OFFSET_MASK 0xFFF8
+ #define IP_PROTOCOL_ICMP 1
+ #define IP_PROTOCOL_IGMP 2
+ #define IP_PROTOCOL_TCP 6
+ #define IP_PROTOCOL_UDP 0x11
+ #define IP_PROTOCOL_IPRAW 0xFF
+
+ #define POLL_IMS_ENABLE_MASK (E1000_IMS_RXDMT0 | E1000_IMS_RXSEQ)
+
+ #define IMS_ENABLE_MASK (E1000_IMS_RXT0 | E1000_IMS_TXDW | E1000_IMS_RXDMT0 |
E1000_IMS_RXSEQ | E1000_IMS_LSC)
+
+ #define E1000_RAR_ENTRIES 16
+
+ typedef struct _E1000_RECEIVE_DESCRIPTOR {
+ E1000_64_BIT_PHYSICAL_ADDRESS BufferAddress;
+
+ USHORT Length;
+ USHORT Csum;
+ UCHAR ReceiveStatus;
+ UCHAR Errors;
+ USHORT Special;
+
+ } E1000_RECEIVE_DESCRIPTOR, *PE1000_RECEIVE_DESCRIPTOR;
+
+ #define MIN_NUMBER_OF_DESCRIPTORS (8)
+ #define MAX_NUMBER_OF_DESCRIPTORS (0xFFF8)
+
+ #define E1000_RXD_STAT_DD (0x01)
+ #define E1000_RXD_STAT_EOP (0x02)
+
+ #define E1000_RXD_STAT_ISL (0x04)
+ #define E1000_RXD_STAT_IXSM (0x04)
+ #define E1000_RXD_STAT_VP (0x08)
+ #define E1000_RXD_STAT_BPDU (0x10)
+ #define E1000_RXD_STAT_TCPCS (0x20)
+ #define E1000_RXD_STAT_IPCS (0x40)
+
+ #define E1000_RXD_STAT_PIF (0x80)
+
+ #define E1000_RXD_ERR_CE (0x01)
+ #define E1000_RXD_ERR_SE (0x02)
+ #define E1000_RXD_ERR_SEQ (0x04)
+
+ #define E1000_RXD_ERR_ICE (0x08)
+
+ #define E1000_RXD_ERR_CXE (0x10)
+
+ #define E1000_RXD_ERR_TCPE (0x20)
+ #define E1000_RXD_ERR_IPE (0x40)
+
+ #define E1000_RXD_ERR_RXE (0x80)
+
+ #define E1000_RXD_ERR_FRAME_ERR_MASK (E1000_RXD_ERR_CE | E1000_RXD_ERR_SE |
E1000_RXD_ERR_SEQ | E1000_RXD_ERR_CXE | E1000_RXD_ERR_RXE)
+
+ #define E1000_RXD_SPC_VLAN_MASK (0x0FFF)
+ #define E1000_RXD_SPC_PRI_MASK (0xE000)
+ #define E1000_RXD_SPC_PRI_SHIFT (0x000D)
+ #define E1000_RXD_SPC_CFI_MASK (0x1000)
+ #define E1000_RXD_SPC_CFI_SHIFT (0x000C)
+
+ #define E1000_TXD_DTYP_D (0x00100000)
+ #define E1000_TXD_DTYP_C (0x00000000)
+ #define E1000_TXD_POPTS_IXSM (0x01)
+ #define E1000_TXD_POPTS_TXSM (0x02)
+
+ typedef struct _E1000_TRANSMIT_DESCRIPTOR {
+ E1000_64_BIT_PHYSICAL_ADDRESS BufferAddress;
+
+ union {
+ ULONG DwordData;
+ struct _TXD_FLAGS {
+ USHORT Length;
+ UCHAR Cso;
+ UCHAR Cmd;
+ } Flags;
+ } Lower;
+
+ union {
+ ULONG DwordData;
+ struct _TXD_FIELDS {
+ UCHAR TransmitStatus;
+ UCHAR Css;
+ USHORT Special;
+ } Fields;
+ } Upper;
+
+ } E1000_TRANSMIT_DESCRIPTOR, *PE1000_TRANSMIT_DESCRIPTOR;
+
+ typedef struct _E1000_TCPIP_CONTEXT_TRANSMIT_DESCRIPTOR {
+ union {
+ ULONG IpXsumConfig;
+ struct _IP_XSUM_FIELDS {
+ UCHAR Ipcss;
+ UCHAR Ipcso;
+ USHORT Ipcse;
+ } IpFields;
+ } LowerXsumSetup;
+
+ union {
+ ULONG TcpXsumConfig;
+ struct _TCP_XSUM_FIELDS {
+ UCHAR Tucss;
+ UCHAR Tucso;
+ USHORT Tucse;
+ } TcpFields;
+ } UpperXsumSetup;
+
+ ULONG CmdAndLength;
+
+ union {
+ ULONG DwordData;
+ struct _TCP_SEG_FIELDS {
+ UCHAR Status;
+ UCHAR HdrLen;
+ USHORT Mss;
+ } Fields;
+ } TcpSegSetup;
+
+ } E1000_TCPIP_CONTEXT_TRANSMIT_DESCRIPTOR,
+ *PE1000_TCPIP_CONTEXT_TRANSMIT_DESCRIPTOR;
+
+ typedef struct _E1000_TCPIP_DATA_TRANSMIT_DESCRIPTOR {
+ E1000_64_BIT_PHYSICAL_ADDRESS BufferAddress;
+
+ union {
+ ULONG DwordData;
+ struct _TXD_OD_FLAGS {
+ USHORT Length;
+ UCHAR TypLenExt;
+ UCHAR Cmd;
+ } Flags;
+ } Lower;
+
+ union {
+ ULONG DwordData;
+ struct _TXD_OD_FIELDS {
+ UCHAR TransmitStatus;
+ UCHAR Popts;
+ USHORT Special;
+ } Fields;
+ } Upper;
+
+ } E1000_TCPIP_DATA_TRANSMIT_DESCRIPTOR,
+ *PE1000_TCPIP_DATA_TRANSMIT_DESCRIPTOR;
+
+ #define E1000_TXD_CMD_EOP (0x01000000)
+ #define E1000_TXD_CMD_IFCS (0x02000000)
+
+ #define E1000_TXD_CMD_IC (0x04000000)
+
+ #define E1000_TXD_CMD_RS (0x08000000)
+ #define E1000_TXD_CMD_RPS (0x10000000)
+
+ #define E1000_TXD_CMD_DEXT (0x20000000)
+ #define E1000_TXD_CMD_ISLVE (0x40000000)
+
+ #define E1000_TXD_CMD_IDE (0x80000000)
+
+ #define E1000_TXD_STAT_DD (0x00000001)
+ #define E1000_TXD_STAT_EC (0x00000002)
+ #define E1000_TXD_STAT_LC (0x00000004)
+ #define E1000_TXD_STAT_TU (0x00000008)
+
+ #define E1000_TXD_CMD_TCP (0x01000000)
+ #define E1000_TXD_CMD_IP (0x02000000)
+ #define E1000_TXD_CMD_TSE (0x04000000)
+
+ #define E1000_TXD_STAT_TC (0x00000004)
+
+ #define E1000_NUM_UNICAST (16)
+ #define E1000_MC_TBL_SIZE (128)
+
+ #define E1000_VLAN_FILTER_TBL_SIZE (128)
+
+ enum {
+ FLOW_CONTROL_NONE = 0,
+ FLOW_CONTROL_RECEIVE_PAUSE = 1,
+ FLOW_CONTROL_TRANSMIT_PAUSE = 2,
+ FLOW_CONTROL_FULL = 3,
+ FLOW_CONTROL_HW_DEFAULT = 0xFF
+ };
+
+ typedef struct {
+ volatile UINT32 Low;
+ volatile UINT32 High;
+ } RECEIVE_ADDRESS_REGISTER_PAIR;
+
+ #define E1000_NUM_MTA_REGISTERS 128
+
+ typedef struct {
+ volatile UINT32 IpAddress;
+ volatile UINT32 Reserved;
+ } IPAT_ENTRY;
+
+ #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX (4)
+ #define E1000_IPAT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
+
+ typedef struct {
+ volatile UINT32 Length;
+ volatile UINT32 Reserved;
+ } FFLT_ENTRY;
+
+ typedef struct {
+ volatile UINT32 Mask;
+ volatile UINT32 Reserved;
+ } FFMT_ENTRY;
+
+ typedef struct {
+ volatile UINT32 Value;
+ volatile UINT32 Reserved;
+ } FFVT_ENTRY;
+
+ #define E1000_FLEXIBLE_FILTER_COUNT_MAX (4)
+
+ #define E1000_FLEXIBLE_FILTER_SIZE_MAX (128)
+
+ #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
+ #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+ #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+
+ typedef struct _E1000_REGISTERS {
+
+ volatile UINT32 Ctrl;
+ volatile UINT32 Pad1;
+ volatile UINT32 Status;
+ volatile UINT32 Pad2;
+ volatile UINT32 Eecd;
+ volatile UINT32 Pad3;
+ volatile UINT32 Exct;
+ volatile UINT32 Pad4;
+ volatile UINT32 Mdic;
+ volatile UINT32 Pad5;
+ volatile UINT32 Fcal;
+ volatile UINT32 Fcah;
+ volatile UINT32 Fct;
+ volatile UINT32 Pad6;
+
+ volatile UINT32 Vet;
+ volatile UINT32 Pad7;
+
+ RECEIVE_ADDRESS_REGISTER_PAIR Rar[16];
+
+ volatile UINT32 Icr;
+ volatile UINT32 Pad8;
+ volatile UINT32 Ics;
+ volatile UINT32 Pad9;
+ volatile UINT32 Ims;
+ volatile UINT32 Pad10;
+ volatile UINT32 Imc;
+ volatile UINT8 Pad11[0x24];
+
+ volatile UINT32 Rctl;
+ volatile UINT32 Pad12;
+ volatile UINT32 PadRdtr0;
+ volatile UINT32 Pad13;
+ volatile UINT32 PadRdbal0;
+ volatile UINT32 PadRdbah0;
+ volatile UINT32 PadRdlen0;
+ volatile UINT32 Pad14;
+ volatile UINT32 PadRdh0;
+ volatile UINT32 Pad15;
+ volatile UINT32 PadRdt0;
+ volatile UINT32 Pad16;
+ volatile UINT32 Rdtr1;
+ volatile UINT32 Pad17;
+ volatile UINT32 Rdbal1;
+ volatile UINT32 Rdbah1;
+ volatile UINT32 Rdlen1;
+ volatile UINT32 Pad18;
+ volatile UINT32 Rdh1;
+ volatile UINT32 Pad19;
+ volatile UINT32 Rdt1;
+ volatile UINT8 Pad20[0x0C];
+ volatile UINT32 PadFcrth;
+ volatile UINT32 Pad21;
+ volatile UINT32 PadFcrtl;
+ volatile UINT32 Pad22;
+ volatile UINT32 Fcttv;
+ volatile UINT32 Pad23;
+ volatile UINT32 Txcw;
+ volatile UINT32 Pad24;
+ volatile UINT32 Rxcw;
+ volatile UINT8 Pad25[0x7C];
+ volatile UINT32 Mta[(128)];
+
+ volatile UINT32 Tctl;
+ volatile UINT32 Pad26;
+ volatile UINT32 Tqsal;
+ volatile UINT32 Tqsah;
+ volatile UINT32 Tipg;
+ volatile UINT32 Pad27;
+ volatile UINT32 Tqc;
+ volatile UINT32 Pad28;
+ volatile UINT32 PadTdbal;
+ volatile UINT32 PadTdbah;
+ volatile UINT32 PadTdl;
+ volatile UINT32 Pad29;
+ volatile UINT32 PadTdh;
+ volatile UINT32 Pad30;
+ volatile UINT32 PadTdt;
+ volatile UINT32 Pad31;
+ volatile UINT32 PadTidv;
+ volatile UINT32 Pad32;
+ volatile UINT32 Tbt;
+ volatile UINT8 Pad33[0x0C];
+
+ volatile UINT32 Ait;
+ volatile UINT8 Pad34[0xA4];
+
+ volatile UINT32 Ftr[8];
+ volatile UINT32 Fcr;
+ volatile UINT32 Pad35;
+ volatile UINT32 Trcr;
+
+ volatile UINT8 Pad36[0xD4];
+
+ volatile UINT32 Vfta[(128)];
+ volatile UINT8 Pad37[0x700];
+ volatile UINT32 Circ;
+ volatile UINT8 Pad37a[0xFC];
+
+ volatile UINT32 Pba;
+ volatile UINT8 Pad38[0xFFC];
+
+ volatile UINT8 Pad39[0x8];
+ volatile UINT32 Ert;
+ volatile UINT8 Pad40[0xf4];
+
+ volatile UINT8 Pad41[0x60];
+ volatile UINT32 Fcrtl;
+ volatile UINT32 Pad42;
+ volatile UINT32 Fcrth;
+ volatile UINT8 Pad43[0x294];
+
+ volatile UINT8 Pad44[0x10];
+ volatile UINT32 Rdfh;
+ volatile UINT32 Pad45;
+ volatile UINT32 Rdft;
+ volatile UINT32 Pad45a;
+ volatile UINT32 Rdfhs;
+ volatile UINT32 Pad45b;
+ volatile UINT32 Rdfts;
+ volatile UINT32 Pad45c;
+ volatile UINT32 Rdfpc;
+ volatile UINT8 Pad46[0x3cc];
+
+ volatile UINT32 Rdbal0;
+ volatile UINT32 Rdbah0;
+ volatile UINT32 Rdlen0;
+ volatile UINT32 Pad47;
+ volatile UINT32 Rdh0;
+ volatile UINT32 Pad48;
+ volatile UINT32 Rdt0;
+ volatile UINT32 Pad49;
+ volatile UINT32 Rdtr0;
+ volatile UINT32 Pad50;
+ volatile UINT32 Rxdctl;
+ volatile UINT32 Pad51;
+ volatile UINT32 Rddh0;
+ volatile UINT32 Pad52;
+ volatile UINT32 Rddt0;
+ volatile UINT8 Pad53[0x7C4];
+
+ volatile UINT32 Txdmac;
+ volatile UINT32 Pad54;
+ volatile UINT32 Ett;
+ volatile UINT8 Pad55[0x3f4];
+
+ volatile UINT8 Pad56[0x10];
+ volatile UINT32 Tdfh;
+ volatile UINT32 Pad57;
+ volatile UINT32 Tdft;
+ volatile UINT32 Pad57a;
+ volatile UINT32 Tdfhs;
+ volatile UINT32 Pad57b;
+ volatile UINT32 Tdfts;
+ volatile UINT32 Pad57c;
+ volatile UINT32 Tdfpc;
+ volatile UINT8 Pad58[0x3cc];
+
+ volatile UINT32 Tdbal;
+ volatile UINT32 Tdbah;
+ volatile UINT32 Tdl;
+ volatile UINT32 Pad59;
+ volatile UINT32 Tdh;
+ volatile UINT32 Pad60;
+ volatile UINT32 Tdt;
+ volatile UINT32 Pad61;
+ volatile UINT32 Tidv;
+ volatile UINT32 Pad62;
+ volatile UINT32 Txdctl;
+ volatile UINT32 Pad63;
+ volatile UINT32 Tddh;
+ volatile UINT32 Pad64;
+ volatile UINT32 Tddt;
+ volatile UINT8 Pad65[0x7C4];
+
+ volatile UINT32 Crcerrs;
+ volatile UINT32 Algnerrc;
+ volatile UINT32 Symerrs;
+ volatile UINT32 Rxerrc;
+ volatile UINT32 Mpc;
+ volatile UINT32 Scc;
+ volatile UINT32 Ecol;
+ volatile UINT32 Mcc;
+ volatile UINT32 Latecol;
+ volatile UINT32 Pad66;
+ volatile UINT32 Colc;
+ volatile UINT32 Tuc;
+ volatile UINT32 Dc;
+ volatile UINT32 Tncrs;
+ volatile UINT32 Sec;
+ volatile UINT32 Cexterr;
+ volatile UINT32 Rlec;
+ volatile UINT32 Rutec;
+ volatile UINT32 Xonrxc;
+ volatile UINT32 Xontxc;
+ volatile UINT32 Xoffrxc;
+ volatile UINT32 Xofftxc;
+ volatile UINT32 Fcruc;
+ volatile UINT32 Prc64;
+ volatile UINT32 Prc127;
+ volatile UINT32 Prc255;
+ volatile UINT32 Prc511;
+ volatile UINT32 Prc1023;
+ volatile UINT32 Prc1522;
+ volatile UINT32 Gprc;
+ volatile UINT32 Bprc;
+ volatile UINT32 Mprc;
+ volatile UINT32 Gptc;
+ volatile UINT32 Pad67;
+ volatile UINT32 Gorl;
+ volatile UINT32 Gorh;
+ volatile UINT32 Gotl;
+ volatile UINT32 Goth;
+ volatile UINT8 Pad68[8];
+ volatile UINT32 Rnbc;
+ volatile UINT32 Ruc;
+ volatile UINT32 Rfc;
+ volatile UINT32 Roc;
+ volatile UINT32 Rjc;
+ volatile UINT8 Pad69[0xC];
+ volatile UINT32 Torl;
+ volatile UINT32 Torh;
+ volatile UINT32 Totl;
+ volatile UINT32 Toth;
+ volatile UINT32 Tpr;
+ volatile UINT32 Tpt;
+ volatile UINT32 Ptc64;
+ volatile UINT32 Ptc127;
+ volatile UINT32 Ptc255;
+ volatile UINT32 Ptc511;
+ volatile UINT32 Ptc1023;
+ volatile UINT32 Ptc1522;
+ volatile UINT32 Mptc;
+ volatile UINT32 Bptc;
+
+ volatile UINT32 Tsctc;
+ volatile UINT32 Tsctfc;
+ volatile UINT8 Pad70[0x0F00];
+
+ volatile UINT32 Rxcsum;
+ volatile UINT8 Pad71[0x07FC];
+
+ volatile UINT32 Wuc;
+ volatile UINT32 Pad72;
+ volatile UINT32 Wufc;
+ volatile UINT32 Pad73;
+ volatile UINT32 Wus;
+ volatile UINT8 Pad74[0x24];
+ volatile UINT32 Ipav;
+ volatile UINT32 Pad75;
+ IPAT_ENTRY Ipat[(4)];
+ volatile UINT8 Pad76[0xA0];
+ volatile UINT32 Wupl;
+ volatile UINT8 Pad77[0xFC];
+ volatile UINT8 Wupm[0x80];
+ volatile UINT8 Pad78[0x480];
+ FFLT_ENTRY Fflt[(4)];
+ volatile UINT8 Pad79[0x20E0];
+
+ volatile UINT32 PadRdfh;
+ volatile UINT32 Pad80;
+ volatile UINT32 PadRdft;
+ volatile UINT32 Pad81;
+ volatile UINT32 PadTdfh;
+ volatile UINT32 Pad82;
+ volatile UINT32 PadTdft;
+ volatile UINT8 Pad83[0xFE4];
+
+ FFMT_ENTRY Ffmt[(128)];
+ volatile UINT8 Pad84[0x0400];
+ FFVT_ENTRY Ffvt[(128)];
+
+ volatile UINT8 Pad85[0x6400];
+
+ volatile UINT32 Pbm[0x4000];
+
+ } E1000_REGISTERS, *PE1000_REGISTERS;
+
+ typedef struct _OLD_REGISTERS {
+
+ volatile UINT32 Ctrl;
+ volatile UINT32 Pad1;
+ volatile UINT32 Status;
+ volatile UINT32 Pad2;
+ volatile UINT32 Eecd;
+ volatile UINT32 Pad3;
+ volatile UINT32 Exct;
+ volatile UINT32 Pad4;
+ volatile UINT32 Mdic;
+ volatile UINT32 Pad5;
+ volatile UINT32 Fcal;
+ volatile UINT32 Fcah;
+ volatile UINT32 Fct;
+ volatile UINT32 Pad6;
+
+ volatile UINT32 Vet;
+ volatile UINT32 Pad7;
+
+ RECEIVE_ADDRESS_REGISTER_PAIR Rar[16];
+
+ volatile UINT32 Icr;
+ volatile UINT32 Pad8;
+ volatile UINT32 Ics;
+ volatile UINT32 Pad9;
+ volatile UINT32 Ims;
+ volatile UINT32 Pad10;
+ volatile UINT32 Imc;
+ volatile UINT8 Pad11[0x24];
+
+ volatile UINT32 Rctl;
+ volatile UINT32 Pad12;
+ volatile UINT32 Rdtr0;
+ volatile UINT32 Pad13;
+ volatile UINT32 Rdbal0;
+ volatile UINT32 Rdbah0;
+ volatile UINT32 Rdlen0;
+ volatile UINT32 Pad14;
+ volatile UINT32 Rdh0;
+ volatile UINT32 Pad15;
+ volatile UINT32 Rdt0;
+ volatile UINT32 Pad16;
+ volatile UINT32 Rdtr1;
+ volatile UINT32 Pad17;
+ volatile UINT32 Rdbal1;
+ volatile UINT32 Rdbah1;
+ volatile UINT32 Rdlen1;
+ volatile UINT32 Pad18;
+ volatile UINT32 Rdh1;
+ volatile UINT32 Pad19;
+ volatile UINT32 Rdt1;
+ volatile UINT8 Pad20[0x0C];
+ volatile UINT32 Fcrth;
+ volatile UINT32 Pad21;
+ volatile UINT32 Fcrtl;
+ volatile UINT32 Pad22;
+ volatile UINT32 Fcttv;
+ volatile UINT32 Pad23;
+ volatile UINT32 Txcw;
+ volatile UINT32 Pad24;
+ volatile UINT32 Rxcw;
+ volatile UINT8 Pad25[0x7C];
+ volatile UINT32 Mta[(128)];
+
+ volatile UINT32 Tctl;
+ volatile UINT32 Pad26;
+ volatile UINT32 Tqsal;
+ volatile UINT32 Tqsah;
+ volatile UINT32 Tipg;
+ volatile UINT32 Pad27;
+ volatile UINT32 Tqc;
+ volatile UINT32 Pad28;
+ volatile UINT32 Tdbal;
+ volatile UINT32 Tdbah;
+ volatile UINT32 Tdl;
+ volatile UINT32 Pad29;
+ volatile UINT32 Tdh;
+ volatile UINT32 Pad30;
+ volatile UINT32 Tdt;
+ volatile UINT32 Pad31;
+ volatile UINT32 Tidv;
+ volatile UINT32 Pad32;
+ volatile UINT32 Tbt;
+ volatile UINT8 Pad33[0x0C];
+
+ volatile UINT32 Ait;
+ volatile UINT8 Pad34[0xA4];
+
+ volatile UINT32 Ftr[8];
+ volatile UINT32 Fcr;
+ volatile UINT32 Pad35;
+ volatile UINT32 Trcr;
+
+ volatile UINT8 Pad36[0xD4];
+
+ volatile UINT32 Vfta[(128)];
+ volatile UINT8 Pad37[0x700];
+ volatile UINT32 Circ;
+ volatile UINT8 Pad37a[0xFC];
+
+ volatile UINT32 Pba;
+ volatile UINT8 Pad38[0xFFC];
+
+ volatile UINT8 Pad39[0x8];
+ volatile UINT32 Ert;
+ volatile UINT8 Pad40[0x1C];
+ volatile UINT32 Rxdctl;
+ volatile UINT8 Pad41[0xFD4];
+
+ volatile UINT32 Txdmac;
+ volatile UINT32 Pad42;
+ volatile UINT32 Ett;
+ volatile UINT8 Pad43[0x1C];
+ volatile UINT32 Txdctl;
+ volatile UINT8 Pad44[0xFD4];
+
+ volatile UINT32 Crcerrs;
+ volatile UINT32 Algnerrc;
+ volatile UINT32 Symerrs;
+ volatile UINT32 Rxerrc;
+ volatile UINT32 Mpc;
+ volatile UINT32 Scc;
+ volatile UINT32 Ecol;
+ volatile UINT32 Mcc;
+ volatile UINT32 Latecol;
+ volatile UINT32 Pad45;
+ volatile UINT32 Colc;
+ volatile UINT32 Tuc;
+ volatile UINT32 Dc;
+ volatile UINT32 Tncrs;
+ volatile UINT32 Sec;
+ volatile UINT32 Cexterr;
+ volatile UINT32 Rlec;
+ volatile UINT32 Rutec;
+ volatile UINT32 Xonrxc;
+ volatile UINT32 Xontxc;
+ volatile UINT32 Xoffrxc;
+ volatile UINT32 Xofftxc;
+ volatile UINT32 Fcruc;
+ volatile UINT32 Prc64;
+ volatile UINT32 Prc127;
+ volatile UINT32 Prc255;
+ volatile UINT32 Prc511;
+ volatile UINT32 Prc1023;
+ volatile UINT32 Prc1522;
+ volatile UINT32 Gprc;
+ volatile UINT32 Bprc;
+ volatile UINT32 Mprc;
+ volatile UINT32 Gptc;
+ volatile UINT32 Pad46;
+ volatile UINT32 Gorl;
+ volatile UINT32 Gorh;
+ volatile UINT32 Gotl;
+ volatile UINT32 Goth;
+ volatile UINT8 Pad47[8];
+ volatile UINT32 Rnbc;
+ volatile UINT32 Ruc;
+ volatile UINT32 Rfc;
+ volatile UINT32 Roc;
+ volatile UINT32 Rjc;
+ volatile UINT8 Pad48[0xC];
+ volatile UINT32 Torl;
+ volatile UINT32 Torh;
+ volatile UINT32 Totl;
+ volatile UINT32 Toth;
+ volatile UINT32 Tpr;
+ volatile UINT32 Tpt;
+ volatile UINT32 Ptc64;
+ volatile UINT32 Ptc127;
+ volatile UINT32 Ptc255;
+ volatile UINT32 Ptc511;
+ volatile UINT32 Ptc1023;
+ volatile UINT32 Ptc1522;
+ volatile UINT32 Mptc;
+ volatile UINT32 Bptc;
+
+ volatile UINT32 Tsctc;
+ volatile UINT32 Tsctfc;
+ volatile UINT8 Pad49[0x0F00];
+
+ volatile UINT32 Rxcsum;
+ volatile UINT8 Pad50[0x07FC];
+
+ volatile UINT32 Wuc;
+ volatile UINT32 Pad51;
+ volatile UINT32 Wufc;
+ volatile UINT32 Pad52;
+ volatile UINT32 Wus;
+ volatile UINT8 Pad53[0x24];
+ volatile UINT32 Ipav;
+ volatile UINT32 Pad54;
+ IPAT_ENTRY Ipat[(4)];
+ volatile UINT8 Pad55[0xA0];
+ volatile UINT32 Wupl;
+ volatile UINT8 Pad56[0xFC];
+ volatile UINT8 Wupm[0x80];
+ volatile UINT8 Pad57[0x480];
+ FFLT_ENTRY Fflt[(4)];
+ volatile UINT8 Pad58[0x20E0];
+
+ volatile UINT32 Rdfh;
+ volatile UINT32 Pad59;
+ volatile UINT32 Rdft;
+ volatile UINT32 Pad60;
+ volatile UINT32 Tdfh;
+ volatile UINT32 Pad61;
+ volatile UINT32 Tdft;
+ volatile UINT32 Pad62;
+ volatile UINT32 Tdfhs;
+ volatile UINT32 Pad63;
+ volatile UINT32 Tdfts;
+ volatile UINT32 Pad64;
+ volatile UINT32 Tdfpc;
+ volatile UINT8 Pad65[0x0FCC];
+
+ FFMT_ENTRY Ffmt[(128)];
+ volatile UINT8 Pad66[0x0400];
+ FFVT_ENTRY Ffvt[(128)];
+
+ volatile UINT8 Pad67[0x6400];
+
+ volatile UINT32 Pbm[0x4000];
+
+ } OLD_REGISTERS, *POLD_REGISTERS;
+
+ #define E1000_EEPROM_SWDPIN0 (0x00000001)
+ #define E1000_EEPROM_LED_LOGIC (0x0020)
+
+ #define E1000_CTRL_FD (0x00000001)
+ #define E1000_CTRL_BEM (0x00000002)
+ #define E1000_CTRL_PRIOR (0x00000004)
+ #define E1000_CTRL_LRST (0x00000008)
+ #define E1000_CTRL_TME (0x00000010)
+ #define E1000_CTRL_SLE (0x00000020)
+ #define E1000_CTRL_ASDE (0x00000020)
+ #define E1000_CTRL_SLU (0x00000040)
+
+ #define E1000_CTRL_ILOS (0x00000080)
+ #define E1000_CTRL_SPD_SEL (0x00000300)
+ #define E1000_CTRL_SPD_10 (0x00000000)
+ #define E1000_CTRL_SPD_100 (0x00000100)
+ #define E1000_CTRL_SPD_1000 (0x00000200)
+ #define E1000_CTRL_BEM32 (0x00000400)
+ #define E1000_CTRL_FRCSPD (0x00000800)
+ #define E1000_CTRL_FRCDPX (0x00001000)
+
+ #define E1000_CTRL_SWDPIN0 (0x00040000)
+ #define E1000_CTRL_SWDPIN1 (0x00080000)
+ #define E1000_CTRL_SWDPIN2 (0x00100000)
+ #define E1000_CTRL_SWDPIN3 (0x00200000)
+ #define E1000_CTRL_SWDPIO0 (0x00400000)
+ #define E1000_CTRL_SWDPIO1 (0x00800000)
+ #define E1000_CTRL_SWDPIO2 (0x01000000)
+ #define E1000_CTRL_SWDPIO3 (0x02000000)
+ #define E1000_CTRL_RST (0x04000000)
+ #define E1000_CTRL_RFCE (0x08000000)
+ #define E1000_CTRL_TFCE (0x10000000)
+
+ #define E1000_CTRL_RTE (0x20000000)
+ #define E1000_CTRL_VME (0x40000000)
+
+ #define E1000_CTRL_PHY_RST (0x80000000)
+
+ #define E1000_STATUS_FD (0x00000001)
+ #define E1000_STATUS_LU (0x00000002)
+ #define E1000_STATUS_TCKOK (0x00000004)
+ #define E1000_STATUS_RBCOK (0x00000008)
+ #define E1000_STATUS_TXOFF (0x00000010)
+ #define E1000_STATUS_TBIMODE (0x00000020)
+ #define E1000_STATUS_SPEED_10 (0x00000000)
+ #define E1000_STATUS_SPEED_100 (0x00000040)
+ #define E1000_STATUS_SPEED_1000 (0x00000080)
+ #define E1000_STATUS_ASDV (0x00000300)
+ #define E1000_STATUS_MTXCKOK (0x00000400)
+ #define E1000_STATUS_PCI66 (0x00000800)
+ #define E1000_STATUS_BUS64 (0x00001000)
+ #define E1000_STATUS_PCIX_MODE (0x00002000)
+ #define E1000_STATUS_PCIX_SPEED (0x0000C000)
+
+ #define E1000_STATUS_PCIX_SPEED_66 (0x00000000)
+ #define E1000_STATUS_PCIX_SPEED_100 (0x00004000)
+ #define E1000_STATUS_PCIX_SPEED_133 (0x00008000)
+
+ #define E1000_EESK (0x00000001)
+ #define E1000_EECS (0x00000002)
+ #define E1000_EEDI (0x00000004)
+ #define E1000_EEDO (0x00000008)
+ #define E1000_FLASH_WRITE_DIS (0x00000010)
+ #define E1000_FLASH_WRITE_EN (0x00000020)
+
+ #define E1000_EXCTRL_GPI_EN0 (0x00000001)
+ #define E1000_EXCTRL_GPI_EN1 (0x00000002)
+ #define E1000_EXCTRL_GPI_EN2 (0x00000004)
+ #define E1000_EXCTRL_GPI_EN3 (0x00000008)
+ #define E1000_EXCTRL_SWDPIN4 (0x00000010)
+ #define E1000_EXCTRL_SWDPIN5 (0x00000020)
+ #define E1000_EXCTRL_SWDPIN6 (0x00000040)
+ #define E1000_EXCTRL_SWDPIN7 (0x00000080)
+ #define E1000_EXCTRL_SWDPIO4 (0x00000100)
+ #define E1000_EXCTRL_SWDPIO5 (0x00000200)
+ #define E1000_EXCTRL_SWDPIO6 (0x00000400)
+ #define E1000_EXCTRL_SWDPIO7 (0x00000800)
+ #define E1000_EXCTRL_ASDCHK (0x00001000)
+ #define E1000_EXCTRL_EE_RST (0x00002000)
+ #define E1000_EXCTRL_IPS (0x00004000)
+ #define E1000_EXCTRL_SPD_BYPS (0x00008000)
+
+ #define E1000_MDI_WRITE (0x04000000)
+ #define E1000_MDI_READ (0x08000000)
+ #define E1000_MDI_READY (0x10000000)
+ #define E1000_MDI_INT (0x20000000)
+ #define E1000_MDI_ERR (0x40000000)
+
+ #define E1000_RAH_RDR (0x40000000)
+ #define E1000_RAH_AV (0x80000000)
+
+ #define E1000_ICR_TXDW (0x00000001)
+ #define E1000_ICR_TXQE (0x00000002)
+ #define E1000_ICR_LSC (0x00000004)
+ #define E1000_ICR_RXSEQ (0x00000008)
+ #define E1000_ICR_RXDMT0 (0x00000010)
+ #define E1000_ICR_RXDMT1 (0x00000020)
+ #define E1000_ICR_RXO (0x00000040)
+ #define E1000_ICR_RXT0 (0x00000080)
+ #define E1000_ICR_RXT1 (0x00000100)
+ #define E1000_ICR_MDAC (0x00000200)
+ #define E1000_ICR_RXCFG (0x00000400)
+ #define E1000_ICR_GPI_EN0 (0x00000800)
+ #define E1000_ICR_GPI_EN1 (0x00001000)
+ #define E1000_ICR_GPI_EN2 (0x00002000)
+ #define E1000_ICR_GPI_EN3 (0x00004000)
+
+ #define E1000_ICS_TXDW E1000_ICR_TXDW
+ #define E1000_ICS_TXQE E1000_ICR_TXQE
+ #define E1000_ICS_LSC E1000_ICR_LSC
+ #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
+ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
+ #define E1000_ICS_RXDMT1 E1000_ICR_RXDMT1
+ #define E1000_ICS_RXO E1000_ICR_RXO
+ #define E1000_ICS_RXT0 E1000_ICR_RXT0
+ #define E1000_ICS_RXT1 E1000_ICR_RXT1
+ #define E1000_ICS_MDAC E1000_ICR_MDAC
+ #define E1000_ICS_RXCFG E1000_ICR_RXCFG
+ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0
+ #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1
+ #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2
+ #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3
+
+ #define E1000_IMS_TXDW E1000_ICR_TXDW
+ #define E1000_IMS_TXQE E1000_ICR_TXQE
+ #define E1000_IMS_LSC E1000_ICR_LSC
+ #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
+ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
+ #define E1000_IMS_RXDMT1 E1000_ICR_RXDMT1
+ #define E1000_IMS_RXO E1000_ICR_RXO
+ #define E1000_IMS_RXT0 E1000_ICR_RXT0
+ #define E1000_IMS_RXT1 E1000_ICR_RXT1
+ #define E1000_IMS_MDAC E1000_ICR_MDAC
+ #define E1000_IMS_RXCFG E1000_ICR_RXCFG
+ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0
+ #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1
+ #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2
+ #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3
+
+ #define E1000_IMC_TXDW E1000_ICR_TXDW
+ #define E1000_IMC_TXQE E1000_ICR_TXQE
+ #define E1000_IMC_LSC E1000_ICR_LSC
+ #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ
+ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0
+ #define E1000_IMC_RXDMT1 E1000_ICR_RXDMT1
+ #define E1000_IMC_RXO E1000_ICR_RXO
+ #define E1000_IMC_RXT0 E1000_ICR_RXT0
+ #define E1000_IMC_RXT1 E1000_ICR_RXT1
+ #define E1000_IMC_MDAC E1000_ICR_MDAC
+ #define E1000_IMC_RXCFG E1000_ICR_RXCFG
+ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0
+ #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1
+ #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2
+ #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3
+
+ #define E1000_TINT_RINT_PCI (E1000_TXDW|E1000_ICR_RXT0)
+ #define E1000_CAUSE_ERR (E1000_ICR_RXSEQ|E1000_ICR_RXO)
+
+ #define E1000_RCTL_RST (0x00000001)
+ #define E1000_RCTL_EN (0x00000002)
+ #define E1000_RCTL_SBP (0x00000004)
+ #define E1000_RCTL_UPE (0x00000008)
+ #define E1000_RCTL_MPE (0x00000010)
+ #define E1000_RCTL_LPE (0x00000020)
+ #define E1000_RCTL_LBM_NO (0x00000000)
+ #define E1000_RCTL_LBM_MAC (0x00000040)
+ #define E1000_RCTL_LBM_SLP (0x00000080)
+ #define E1000_RCTL_LBM_TCVR (0x000000c0)
+ #define E1000_RCTL_RDMTS0_HALF (0x00000000)
+ #define E1000_RCTL_RDMTS0_QUAT (0x00000100)
+ #define E1000_RCTL_RDMTS0_EIGTH (0x00000200)
+ #define E1000_RCTL_RDMTS1_HALF (0x00000000)
+ #define E1000_RCTL_RDMTS1_QUAT (0x00000400)
+ #define E1000_RCTL_RDMTS1_EIGTH (0x00000800)
+ #define E1000_RCTL_MO_SHIFT 12
+
+ #define E1000_RCTL_MO_0 (0x00000000)
+ #define E1000_RCTL_MO_1 (0x00001000)
+ #define E1000_RCTL_MO_2 (0x00002000)
+ #define E1000_RCTL_MO_3 (0x00003000)
+
+ #define E1000_RCTL_MDR (0x00004000)
+ #define E1000_RCTL_BAM (0x00008000)
+
+ #define E1000_RCTL_SZ_2048 (0x00000000)
+ #define E1000_RCTL_SZ_1024 (0x00010000)
+ #define E1000_RCTL_SZ_512 (0x00020000)
+ #define E1000_RCTL_SZ_256 (0x00030000)
+
+ #define E1000_RCTL_SZ_16384 (0x00010000)
+ #define E1000_RCTL_SZ_8192 (0x00020000)
+ #define E1000_RCTL_SZ_4096 (0x00030000)
+
+ #define E1000_RCTL_VFE (0x00040000)
+
+ #define E1000_RCTL_CFIEN (0x00080000)
+ #define E1000_RCTL_CFI (0x00100000)
+ #define E1000_RCTL_ISLE (0x00200000)
+
+ #define E1000_RCTL_DPF (0x00400000)
+ #define E1000_RCTL_PMCF (0x00800000)
+
+ #define E1000_RCTL_SISLH (0x01000000)
+
+ #define E1000_RCTL_BSEX (0x02000000)
+ #define E1000_RDT0_DELAY (0x0000ffff)
+ #define E1000_RDT0_FPDB (0x80000000)
+
+ #define E1000_RDT1_DELAY (0x0000ffff)
+ #define E1000_RDT1_FPDB (0x80000000)
+
+ #define E1000_RDLEN0_LEN (0x0007ff80)
+
+ #define E1000_RDLEN1_LEN (0x0007ff80)
+
+ #define E1000_RDH0_RDH (0x0000ffff)
+
+ #define E1000_RDH1_RDH (0x0000ffff)
+
+ #define E1000_RDT0_RDT (0x0000ffff)
+
+ #define E1000_FCRTH_RTH (0x0000FFF8)
+ #define E1000_FCRTH_XFCE (0x80000000)
+
+ #define E1000_FCRTL_RTL (0x0000FFF8)
+ #define E1000_FCRTL_XONE (0x80000000)
+
+ #define E1000_RXDCTL_PTHRESH 0x0000003F
+ #define E1000_RXDCTL_HTHRESH 0x00003F00
+ #define E1000_RXDCTL_WTHRESH 0x003F0000
+ #define E1000_RXDCTL_GRAN 0x01000000
+
+ #define E1000_TXDCTL_PTHRESH 0x000000FF
+ #define E1000_TXDCTL_HTHRESH 0x0000FF00
+ #define E1000_TXDCTL_WTHRESH 0x00FF0000
+ #define E1000_TXDCTL_GRAN 0x01000000
+
+ #define E1000_TXCW_FD (0x00000020)
+ #define E1000_TXCW_HD (0x00000040)
+ #define E1000_TXCW_PAUSE (0x00000080)
+ #define E1000_TXCW_ASM_DIR (0x00000100)
+ #define E1000_TXCW_PAUSE_MASK (0x00000180)
+ #define E1000_TXCW_RF (0x00003000)
+ #define E1000_TXCW_NP (0x00008000)
+ #define E1000_TXCW_CW (0x0000ffff)
+ #define E1000_TXCW_TXC (0x40000000)
+ #define E1000_TXCW_ANE (0x80000000)
+
+ #define E1000_RXCW_CW (0x0000ffff)
+ #define E1000_RXCW_NC (0x04000000)
+ #define E1000_RXCW_IV (0x08000000)
+ #define E1000_RXCW_CC (0x10000000)
+ #define E1000_RXCW_C (0x20000000)
+ #define E1000_RXCW_SYNCH (0x40000000)
+ #define E1000_RXCW_ANC (0x80000000)
+
+ #define E1000_TCTL_RST (0x00000001)
+ #define E1000_TCTL_EN (0x00000002)
+ #define E1000_TCTL_BCE (0x00000004)
+ #define E1000_TCTL_PSP (0x00000008)
+ #define E1000_TCTL_CT (0x00000ff0)
+ #define E1000_TCTL_COLD (0x003ff000)
+ #define E1000_TCTL_SWXOFF (0x00400000)
+ #define E1000_TCTL_PBE (0x00800000)
+ #define E1000_TCTL_RTLC (0x01000000)
+ #define E1000_TCTL_NRTU (0x02000000)
+
+ #define E1000_TQSAL_TQSAL (0xffffffc0)
+ #define E1000_TQSAH_TQSAH (0xffffffff)
+
+ #define E1000_TQC_SQ (0x00000001)
+ #define E1000_TQC_RQ (0x00000002)
+
+ #define E1000_TDBAL_TDBAL (0xfffff000)
+ #define E1000_TDBAH_TDBAH (0xffffffff)
+
+ #define E1000_TDL_LEN (0x0007ff80)
+
+ #define E1000_TDH_TDH (0x0000ffff)
+
+ #define E1000_TDT_TDT (0x0000ffff)
+
+ #define E1000_RXCSUM_PCSS (0x000000ff)
+ #define E1000_RXCSUM_IPOFL (0x00000100)
+ #define E1000_RXCSUM_TUOFL (0x00000200)
+
+ #define E1000_WUC_APME (0x00000001)
+ #define E1000_WUC_PME_EN (0x00000002)
+ #define E1000_WUC_PME_STATUS (0x00000004)
+ #define E1000_WUC_APMPME (0x00000008)
+
+ #define E1000_WUFC_LNKC (0x00000001)
+ #define E1000_WUFC_MAG (0x00000002)
+ #define E1000_WUFC_EX (0x00000004)
+ #define E1000_WUFC_MC (0x00000008)
+ #define E1000_WUFC_BC (0x00000010)
+ #define E1000_WUFC_ARP (0x00000020)
+ #define E1000_WUFC_IP (0x00000040)
+ #define E1000_WUFC_FLX0 (0x00010000)
+ #define E1000_WUFC_FLX1 (0x00020000)
+ #define E1000_WUFC_FLX2 (0x00040000)
+ #define E1000_WUFC_FLX3 (0x00080000)
+ #define E1000_WUFC_ALL_FILTERS (0x000F007F)
+
+ #define E1000_WUFC_FLX_OFFSET (16)
+ #define E1000_WUFC_FLX_FILTERS (0x000F0000)
+
+ #define E1000_WUS_LNKC (0x00000001)
+ #define E1000_WUS_MAG (0x00000002)
+ #define E1000_WUS_EX (0x00000004)
+ #define E1000_WUS_MC (0x00000008)
+ #define E1000_WUS_BC (0x00000010)
+ #define E1000_WUS_ARP (0x00000020)
+ #define E1000_WUS_IP (0x00000040)
+ #define E1000_WUS_FLX0 (0x00010000)
+ #define E1000_WUS_FLX1 (0x00020000)
+ #define E1000_WUS_FLX2 (0x00040000)
+ #define E1000_WUS_FLX3 (0x00080000)
+ #define E1000_WUS_FLX_FILTERS (0x000F0000)
+
+ #define E1000_WUPL_LENGTH_MASK (0x0FFF)
+
+ /* use old register MacType < MAC_LIVENGOOD */
+
+ #if MACTYPE >= MAC_LIVENGOOD
+
+ # define E1000_WRITE_REG(reg, value) (writel(value,
&((PE1000_REGISTERS)ioaddr)->reg) )
+ # define E1000_READ_REG(reg) (readl(&((PE1000_REGISTERS)ioaddr)->reg))
+
+ #else
+
+ # define E1000_WRITE_REG(reg, value) (writel(value,
&((POLD_REGISTERS)ioaddr)->reg))
+ # define E1000_READ_REG(reg) (readl(&((POLD_REGISTERS)ioaddr)->reg))
+
+ #endif
+
+
+ #define E1000_MDALIGN (4096)
+
+ #define EEPROM_READ_OPCODE (0x6)
+ #define EEPROM_WRITE_OPCODE (0x5)
+ #define EEPROM_ERASE_OPCODE (0x7)
+ #define EEPROM_EWEN_OPCODE (0x13)
+ #define EEPROM_EWDS_OPCODE (0x10)
+
+ #define EEPROM_INIT_CONTROL1_REG (0x000A)
+ #define EEPROM_INIT_CONTROL2_REG (0x000F)
+ #define EEPROM_CHECKSUM_REG (0x003F)
+
+ #define EEPROM_WORD0A_ILOS (0x0010)
+ #define EEPROM_WORD0A_SWDPIO (0x01E0)
+ #define EEPROM_WORD0A_LRST (0x0200)
+ #define EEPROM_WORD0A_FD (0x0400)
+ #define EEPROM_WORD0A_66MHZ (0x0800)
+
+ #define EEPROM_WORD0F_PAUSE_MASK (0x3000)
+ #define EEPROM_WORD0F_PAUSE (0x1000)
+ #define EEPROM_WORD0F_ASM_DIR (0x2000)
+ #define EEPROM_WORD0F_ANE (0x0800)
+ #define EEPROM_WORD0F_SWPDIO_EXT (0x00F0)
+
+ #define EEPROM_SUM (0xBABA)
+
+ #define EEPROM_NODE_ADDRESS_BYTE_0 (0)
+ #define EEPROM_PBA_BYTE_1 (8)
+
+ #define EEPROM_WORD_SIZE (64)
+
+ #define NODE_ADDRESS_SIZE (6)
+ #define PBA_SIZE (4)
+
+ #define E1000_COLLISION_THRESHOLD 16
+ #define E1000_CT_SHIFT 4
+
+ #define E1000_FDX_COLLISION_DISTANCE 64
+ #define E1000_HDX_COLLISION_DISTANCE 64
+ #define E1000_GB_HDX_COLLISION_DISTANCE 512
+ #define E1000_COLD_SHIFT 12
+
+ #define REQ_TX_DESCRIPTOR_MULTIPLE 8
+ #define REQ_RX_DESCRIPTOR_MULTIPLE 8
+
+ #define DEFAULT_WSMN_TIPG_IPGT 10
+
+ #define DEFAULT_LVGD_TIPG_IPGT_FIBER 6
+ #define DEFAULT_LVGD_TIPG_IPGT_COPPER 8
+
+ #define E1000_TIPG_IPGT_MASK 0x000003FF
+ #define E1000_TIPG_IPGR1_MASK 0x000FFC00
+ #define E1000_TIPG_IPGR2_MASK 0x3FF00000
+
+ #define DEFAULT_WSMN_TIPG_IPGR1 2
+ #define DEFAULT_LVGD_TIPG_IPGR1 8
+ #define E1000_TIPG_IPGR1_SHIFT 10
+
+ #define DEFAULT_WSMN_TIPG_IPGR2 10
+ #define DEFAULT_LVGD_TIPG_IPGR2 6
+ #define E1000_TIPG_IPGR2_SHIFT 20
+
+ #define E1000_TXDMAC_DPP 0x00000001
+
+ #define FLOW_CONTROL_ADDRESS_LOW (0x00C28001)
+ #define FLOW_CONTROL_ADDRESS_HIGH (0x00000100)
+ #define FLOW_CONTROL_TYPE (0x8808)
+
+ #define FC_DEFAULT_HI_THRESH (0x8000)
+ #define FC_DEFAULT_LO_THRESH (0x4000)
+ #define FC_DEFAULT_TX_TIMER (0x100)
+
+ #define PAUSE_SHIFT 5
+
+ #define SWDPIO_SHIFT 17
+
+ #define SWDPIO__EXT_SHIFT 4
+
+ #define ILOS_SHIFT 3
+
+ #define MDI_REGADD_SHIFT 16
+
+ #define MDI_PHYADD_SHIFT 21
+
+ #define RECEIVE_BUFFER_ALIGN_SIZE (256)
+
+ #define LINK_UP_TIMEOUT 500
+
+ #define E1000_TX_BUFFER_SIZE ((UINT)1514)
+
+ #define E1000_MIN_SIZE_OF_RECEIVE_BUFFERS (2048)
+
+ #define E1000_SIZE_OF_RECEIVE_BUFFERS (2048)
+
+ #define E1000_SIZE_OF_UNALIGNED_RECEIVE_BUFFERS
E1000_SIZE_OF_RECEIVE_BUFFERS+RECEIVE_BUFFER_ALIGN_SIZE
+
+ #define COALESCE_BUFFER_SIZE 0x800
+ #define COALESCE_BUFFER_ALIGN 0x800
+
+ #define CARRIER_EXTENSION 0x0F
+
+ #define TBI_ACCEPT(RxErrors, LastByteInFrame, HwFrameLength)
(Adapter->TbiCompatibilityOn &&
(((RxErrors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE)&&
((LastByteInFrame) == CARRIER_EXTENSION) &&
((HwFrameLength) > 64) &&
((HwFrameLength) <= Adapter->MaxFrameSize+1))
+
+ #define E1000_WAIT_PERIOD 10
+
+ #endif /* _FXHW_ */
+
diff -rc2P -x '*~' grub-0.93/netboot/e1000.h grub-0.93-e1000/netboot/e1000.h
*** grub-0.93/netboot/e1000.h 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000.h 2003-03-14 16:56:25.000000000 +0000
***************
*** 0 ****
--- 1,398 ----
+ /*****************************************************************************
+ *****************************************************************************
+
+ Copyright (c) 1999-2001 Intel Corporation.
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the
documentation
+ and/or other materials provided with the distribution.
+
+ 3. Neither the name of Intel Corporation nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ *****************************************************************************
+
*****************************************************************************/
+
+ /*************************************************************************/
+ /*! \file e1000.h
+ * \author Intel Corporation
+ * \date 1999-2001
+ * \brief Linux PRO/1000 Ethernet Driver main header file
+ *************************************************************************/
+
+ #ifndef _E1000_H_
+ #define _E1000_H_
+
+ struct _ADAPTER_STRUCT;
+ typedef struct _ADAPTER_STRUCT ADAPTER_STRUCT, *PADAPTER_STRUCT;
+
+
+ /* Prevent name space polution */
+
+ #define IN
+ #define OUT
+ #define STATIC static
+
+ #include "e1000_fxhw.h"
+ #include "e1000_phy.h"
+
+
+ #define PCI_DEVICE_ID_82542 0x1000
+ #define PCI_DEVICE_ID_82543GC_FIBER 0x1001
+ #define PCI_DEVICE_ID_82543GC_COPPER 0x1004
+ #define PCI_DEVICE_ID_82544EI_COPPER 0x1008
+ #define PCI_DEVICE_ID_82544GC_CREB 0x100D
+ #define BAR_0 0
+
+ /* 8254x can use Dual Address Cycles for 64-bit addressing */
+ /* Advertise that we can DMA from any address location */
+ #define E1000_DMA_MASK (~0x0UL)
+ #define E1000_DBG(args...)
+ // #define E1000_DBG(args...) printk("e1000: " args)
+ #define E1000_ERR(args...) printf("e1000: " args)
+ #define E1000_MAX_INTR 10
+ #define MAX_NUM_MULTICAST_ADDRESSES 128
+
+ #define B_TRUE 1
+ #define B_FALSE 0
+ #define TRUE 1
+ #define FALSE 0
+
+ /* command line options defaults */
+ #define DEFAULT_TXD 256
+ #define MAX_TXD 256
+ #define MIN_TXD 80
+ #define DEFAULT_RXD 256
+ #define MAX_RXD 256
+ #define MIN_RXD 80
+ #define DEFAULT_TIDV 64
+ #define MAX_TIDV 0xFFFF
+ #define MIN_TIDV 0
+ #define DEFAULT_RIDV 64
+ #define MAX_RIDV 0xFFFF
+ #define MIN_RIDV 0
+
+ #define OPTION_UNSET -1
+ #define OPTION_DISABLED 0
+ #define OPTION_ENABLED 1
+ #define JUMBO_DEFAULT OPTION_ENABLED
+ #define XSUMRX_DEFAULT OPTION_ENABLED
+ #define WAITFORLINK_DEFAULT OPTION_ENABLED
+ #define AUTONEG_ADV_DEFAULT 0x2F
+ #define AUTONEG_ADV_MASK 0x2F
+ #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
+
+ #define E1000_REPORT_TX_EARLY 2
+ #define E1000_PCI_MWI_ENABLE 1
+ #define E1000_PCI_MLT_OVERRIDE 0
+
+ #define E1000_BUS_TYPE_PCI 1
+ #define E1000_BUS_TYPE_PCIX 2
+
+ #define E1000_BUS_SPEED_PCI_33MHZ 1
+ #define E1000_BUS_SPEED_PCI_66MHZ 2
+ #define E1000_BUS_SPEED_PCIX_50_66MHZ 3
+ #define E1000_BUS_SPEED_PCIX_66_100MHZ 4
+ #define E1000_BUS_SPEED_PCIX_100_133MHZ 5
+ #define E1000_BUS_SPEED_PCIX_RESERVED 6
+
+ #define E1000_BUS_WIDTH_32_BIT 1
+ #define E1000_BUS_WIDTH_64_BIT 2
+
+ /* Supported RX Buffer Sizes */
+ #define E1000_RXBUFFER_2048 2048
+ #define E1000_RXBUFFER_4096 4096
+ #define E1000_RXBUFFER_8192 8192
+ #define E1000_RXBUFFER_16384 16384
+
+ #define ETH_LENGTH_OF_ADDRESS 6
+
+ #define RET_STATUS_SUCCESS 0
+ #define RET_STATUS_FAILURE 1
+
+ #define E1000_PCI
+
+ /* The size in bytes of a standard ethernet header */
+ #define ENET_HEADER_SIZE 14
+ #define MAX_INTS 256
+ #define CRC_LENGTH 4
+
+ #define MAXIMUM_ETHERNET_PACKET_SIZE 1514
+ #define RCV_PKT_MUL 5
+
+ /* Round size up to the next multiple of unit */
+ #define E1000_ROUNDUP(size, unit) ((((size) + (unit) - 1) / (unit)) * (unit))
+ /* This is better, but only works for unit sizes that are powers of 2 */
+ #define E1000_ROUNDUP2(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
+
+ /* wrapper around a pointer to a socket buffer,
+ * so a DMA handle can be stored along with the buffer */
+ #if 0
+ struct e1000_buffer {
+ struct sk_buff *skb;
+ uint64_t dma;
+ unsigned long length;
+ };
+ #endif
+
+ /* Adapter->flags definitions */
+ #define E1000_BOARD_OPEN 0
+
+ typedef enum _XSUM_CONTEXT_T {
+ OFFLOAD_NONE,
+ OFFLOAD_TCP_IP,
+ OFFLOAD_UDP_IP
+ } XSUM_CONTEXT_T;
+
+ /* board specific private data structure */
+
+ struct _ADAPTER_STRUCT {
+ struct _ADAPTER_STRUCT *next;
+ struct _ADAPTER_STRUCT *prev;
+
+ #ifdef IANS
+ void *iANSReserved;
+ piANSsupport_t iANSdata;
+ UINT32 ans_link;
+ UINT32 ans_speed;
+ UINT32 ans_duplex;
+ UINT32 ans_suspend;
+ IANS_BD_TAGGING_MODE tag_mode;
+ #endif
+
+ /* MMIO PCI Registers */
+ volatile PE1000_REGISTERS HardwareVirtualAddress;
+
+
+ uint32_t flags;
+ uint32_t bd_number;
+
+ /* Ethernet Node Address */
+ uint8_t CurrentNetAddress[ETH_LENGTH_OF_ADDRESS];
+ uint8_t PermNetAddress[ETH_LENGTH_OF_ADDRESS];
+
+ /* Mac and Phy Settings */
+ uint8_t MacType;
+ uint8_t MediaType;
+ uint32_t PhyId;
+ uint32_t PhyAddress;
+
+ /* MAC Configuration */
+ uint8_t AutoNeg;
+ uint8_t ForcedSpeedDuplex;
+ uint16_t AutoNegAdvertised;
+ uint8_t WaitAutoNegComplete;
+
+ /* Status Flags */
+ BOOLEAN LinkIsActive;
+ uint16_t LineSpeed;
+ uint16_t FullDuplex;
+ BOOLEAN GetLinkStatus;
+ BOOLEAN LinkStatusChanged;
+ BOOLEAN LongPacket;
+ uint32_t RxBufferLen;
+ BOOLEAN TbiCompatibilityEnable;
+ BOOLEAN TbiCompatibilityOn;
+
+ /* PCI Device Info */
+ uint16_t VendorId;
+ uint16_t DeviceId;
+ uint8_t RevId;
+ uint16_t SubVendorId;
+ uint16_t SubSystemId;
+
+ /* PCI Bus Info */
+ uint8_t BusType;
+ uint8_t BusSpeed;
+ uint8_t BusWidth;
+
+ UINT32 PartNumber;
+
+ BOOLEAN NosEnabledMulticastPromiscuous;
+
+ BOOLEAN AdapterStopped;
+ uint32_t IntMask;
+ uint16_t PciCommandWord;
+ uint8_t DmaFairness;
+ uint32_t OriginalFlowControl;
+ uint8_t FlowControl;
+ uint16_t FlowControlHighWatermark;
+ uint16_t FlowControlLowWatermark;
+ uint16_t FlowControlPauseTime;
+ BOOLEAN FlowControlSendXon;
+ BOOLEAN ReportTxEarly;
+ uint32_t TxcwRegValue;
+ uint32_t AutoNegFailed;
+
+ UINT32 MaxFrameSize;
+ #if 0
+ /* e1000_adaptive */
+ BOOLEAN AdaptiveTxThreshold;
+ UINT32 CurrentTxThreshold;
+ UINT8 TxThresholdTimer;
+ BOOLEAN AdaptiveIFS;
+ BOOLEAN InIFSMode;
+ BOOLEAN IFSParamsForced;
+ UINT16 CurrentIFSValue;
+ UINT16 IFSMaxValue;
+ UINT16 IFSMinValue;
+ UINT16 IFSStepSize;
+ UINT16 IFSRatio;
+ #endif
+ struct pci_device *pdev;
+ /* driver specific */
+
+ int NumTxDescriptors;
+ uint32_t TxIntDelay;
+ int NextAvailTxDescriptor;
+ int OldestUsedTxDescriptor;
+ E1000_TRANSMIT_DESCRIPTOR *TxDescriptors;
+ dma_addr_t TxDescDMA;
+ struct e1000_buffer *tx_skb;
+ u32 NumTxDescriptorsAvail;
+ uint32_t TxdCmd;
+
+ int NumRxDescriptors;
+ uint32_t RxIntDelay;
+ int NextRxDescriptorToCheck;
+ E1000_RECEIVE_DESCRIPTOR *RxDescriptors;
+ dma_addr_t RxDescDMA;
+ struct e1000_buffer *rx_skb;
+ atomic_t NumRxDescriptorsEmpty;
+ int NextRxDescriptorToFill;
+ atomic_t tx_timeout;
+
+ uint64_t XsumRXGood;
+ uint64_t XsumRXError;
+
+ /* Linux driver specific */
+ char *id_string;
+ uint8_t JumboFrames;
+ uint8_t RxChecksum;
+ XSUM_CONTEXT_T ActiveChecksumContext;
+
+ /* Multicast Stuff */
+ UINT32 MulticastFilterType;
+ UINT32 NumberOfMcAddresses;
+ UCHAR
MulticastAddressList[MAX_NUM_MULTICAST_ADDRESSES][ETH_LENGTH_OF_ADDRESS];
+ /* calling these out as unsigned longs helps match up with the OS
+ * stats, which as unsigned longs change from 32 to 64 bits when moving
+ * to a 64-bit CPU, that change should not effect us */
+
+ /* statistic registers present in the 82542 */
+ unsigned long Crcerrs;
+ unsigned long Symerrs;
+ unsigned long Mpc;
+ unsigned long Scc;
+ unsigned long Ecol;
+ unsigned long Mcc;
+ unsigned long Latecol;
+ unsigned long Colc;
+ unsigned long Dc;
+ unsigned long Sec;
+ unsigned long Rlec;
+ unsigned long Xonrxc;
+ unsigned long Xontxc;
+ unsigned long Xoffrxc;
+ unsigned long Xofftxc;
+ unsigned long Fcruc;
+ unsigned long Prc64;
+ unsigned long Prc127;
+ unsigned long Prc255;
+ unsigned long Prc511;
+ unsigned long Prc1023;
+ unsigned long Prc1522;
+ unsigned long Gprc;
+ unsigned long Bprc;
+ unsigned long Mprc;
+ unsigned long Gptc;
+ unsigned long Gorcl;
+ unsigned long Gorch;
+ unsigned long Gotcl;
+ unsigned long Gotch;
+ unsigned long Rnbc;
+ unsigned long Ruc;
+ unsigned long Rfc;
+ unsigned long Roc;
+ unsigned long Rjc;
+ unsigned long Torcl;
+ unsigned long Torch;
+ unsigned long Totcl;
+ unsigned long Totch;
+ unsigned long Tpr;
+ unsigned long Tpt;
+ unsigned long Ptc64;
+ unsigned long Ptc127;
+ unsigned long Ptc255;
+ unsigned long Ptc511;
+ unsigned long Ptc1023;
+ unsigned long Ptc1522;
+ unsigned long Mptc;
+ unsigned long Bptc;
+ /* statistic registers added in the 82543 */
+ unsigned long Algnerrc;
+ unsigned long Rxerrc;
+ unsigned long Tuc;
+ unsigned long Tncrs;
+ unsigned long Cexterr;
+ unsigned long Rutec;
+ unsigned long Tsctc;
+ unsigned long Tsctfc;
+ };
+
+ /* PCI defines needed by e1000_fxhw.c */
+ /* define these using the Linux names for the same thing (pci.h) */
+ #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
+ #define PCI_COMMAND_REGISTER PCI_COMMAND
+
+ /* Prototypes */
+ /* e1000_main.c */
+ /* e1000_fxhw.c */
+ extern VOID AdapterStop(void);
+ extern BOOLEAN InitializeHardware(void);
+ extern VOID InitRxAddresses(void);
+ extern BOOLEAN SetupFlowControlAndLink(void);
+ extern BOOLEAN SetupPcsLink(UINT32 DeviceControlReg);
+ extern VOID ConfigFlowControlAfterLinkUp(void);
+ extern VOID ForceMacFlowControlSetting(void);
+ extern VOID CheckForLink(void);
+ extern VOID ClearHwStatsCounters(void);
+ extern VOID GetSpeedAndDuplex(PUINT16 Speed, PUINT16 Duplex);
+ extern USHORT ReadEepromWord(USHORT Reg);
+ extern BOOLEAN ValidateEepromChecksum(void);
+ extern VOID UpdateEepromChecksum(void);
+ extern BOOLEAN WriteEepromWord(USHORT Reg, USHORT Data);
+ extern UINT32 ReadPartNumber(void);
+ extern VOID IdLedOn(void);
+ extern VOID IdLedOff(void);
+ extern VOID MulticastAddressListUpdate(PUCHAR MulticastAddressList,
+ UINT32 MulticastAddressCount, UINT32 Padding);
+ extern VOID AdjustTbiAcceptedStats(UINT32 FrameLength, PUINT8 MacAddress);
+ extern VOID WriteVfta(UINT32 Offset, UINT32 Value);
+ extern VOID ClearVfta(void);
+
+ /* e1000_phy.h */
+ extern UINT16 ReadPhyRegister(UINT32 RegAddress, UINT32 PhyAddress);
+ extern VOID PhyHardwareReset(void);
+ /* #include "e1000_adaptive.h" */
+ #endif /* _E1000_H_ */
diff -rc2P -x '*~' grub-0.93/netboot/e1000_ids.h
grub-0.93-e1000/netboot/e1000_ids.h
*** grub-0.93/netboot/e1000_ids.h 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000_ids.h 2003-03-14 12:21:42.000000000 +0000
***************
*** 0 ****
--- 1,7 ----
+ static struct pci_id e1000_nics[] = {
+ { 0x8086,0x1000, "Intel EtherExpressPro1000" },
+ { 0x8086,0x1001, "Intel EtherExpressPro1000 82543GC Fiber" },
+ { 0x8086,0x1004, "Intel EtherExpressPro1000 82543GC Copper" },
+ { 0x8086,0x1008, "Intel EtherExpressPro1000 82544EI Copper" },
+ { 0x8086,0x100d, "Intel EtherExpressPro1000 82544GC Creb" },
+ };
diff -rc2P -x '*~' grub-0.93/netboot/e1000_phy.c
grub-0.93-e1000/netboot/e1000_phy.c
*** grub-0.93/netboot/e1000_phy.c 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000_phy.c 2003-03-14 12:21:42.000000000 +0000
***************
*** 0 ****
--- 1,969 ----
+ /*****************************************************************************
+ *****************************************************************************
+
+ Copyright (c) 1999 - 2001, Intel Corporation
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the
documentation
+ and/or other materials provided with the distribution.
+
+ 3. Neither the name of Intel Corporation nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ *****************************************************************************
+
*****************************************************************************/
+
+ /* Workfile: phy.c */
+ /* Revision: 31 */
+ /* Date: 8/03/01 10:39a */
+
+ #include "e1000.h"
+
+ #define GOOD_MII_IF 0
+
+ UINT16
+ ReadPhyRegister(IN UINT32 RegAddress, IN UINT32 PhyAddress);
+
+ VOID
+ WritePhyRegister(IN UINT32 RegAddress,
+ IN UINT32 PhyAddress, IN UINT16 Data);
+
+ STATIC
+ VOID
+ MIIShiftOutPhyData(IN UINT32 Data, IN UINT16 Count);
+
+ STATIC
+ VOID
+ RaiseMdcClock(IN OUT UINT32 * CtrlRegValue);
+
+ STATIC
+ VOID
+ LowerMdcClock(IN OUT UINT32 * CtrlRegValue);
+
+ STATIC UINT16 MIIShiftInPhyData(void);
+
+ VOID PhyHardwareReset(void);
+
+ BOOLEAN PhyReset(void);
+
+ BOOLEAN PhySetup(IN UINT32 DeviceControlReg);
+
+ STATIC BOOLEAN PhySetupAutoNegAdvertisement(void);
+
+ STATIC VOID PhyForceSpeedAndDuplex(void);
+
+ VOID
+ ConfigureMacToPhySettings(IN UINT16 MiiRegisterData);
+
+ VOID ConfigureCollisionDistance(void);
+
+ VOID DisplayMiiContents(IN UINT8 PhyAddress);
+
+ UINT32 AutoDetectGigabitPhy(void);
+
+ VOID PxnPhyResetDsp(void);
+
+ VOID PxnIntegratedPhyLoopback(IN UINT16 Speed);
+
+ VOID PxnPhyEnableReceiver(void);
+
+ VOID PxnPhyDisableReceiver(void);
+
+ BOOLEAN WaitForAutoNeg(void);
+
+ UINT16
+ ReadPhyRegister(IN UINT32 RegAddress, IN UINT32 PhyAddress)
+ {
+ UINT32 i;
+ UINT32 Data;
+ UINT32 Command = 0;
+
+ ASSERT(RegAddress <= MAX_PHY_REG_ADDRESS);
+
+ #if (MACTYPE > MAC_LIVENGOOD)
+
+ Command = ((RegAddress << MDI_REGADD_SHIFT) |
+ (PhyAddress << MDI_PHYADD_SHIFT) | (E1000_MDI_READ));
+
+ E1000_WRITE_REG(Mdic, Command);
+
+ for (i = 0; i < 10; i++) {
+ DelayInMicroseconds(10);
+
+ Data = E1000_READ_REG(Mdic);
+
+ if (Data & E1000_MDI_READY)
+ break;
+ }
+ #else
+
+ MIIShiftOutPhyData(PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+ Command = ((RegAddress) |
+ (PhyAddress << 5) |
+ (PHY_OP_READ << 10) | (PHY_SOF << 12));
+
+ MIIShiftOutPhyData(Command, 14);
+
+ Data = (UINT32) MIIShiftInPhyData();
+ #endif
+
+ ASSERT(!(Data & E1000_MDI_ERR));
+
+ return ((UINT16) Data);
+ }
+
+ VOID
+ WritePhyRegister(IN UINT32 RegAddress,
+ IN UINT32 PhyAddress, IN UINT16 Data)
+ {
+ UINT32 i;
+ UINT32 Command = 0;
+ UINT32 MdicRegValue;
+
+ ASSERT(RegAddress <= MAX_PHY_REG_ADDRESS);
+
+ # if (MACTYPE > MAC_LIVENGOOD)
+
+ Command = (((UINT32) Data) |
+ (RegAddress << MDI_REGADD_SHIFT) |
+ (PhyAddress << MDI_PHYADD_SHIFT) | (E1000_MDI_WRITE));
+
+ E1000_WRITE_REG(Mdic, Command);
+
+ for (i = 0; i < 10; i++) {
+ DelayInMicroseconds(10);
+
+ MdicRegValue = E1000_READ_REG(Mdic);
+
+ if (MdicRegValue & E1000_MDI_READY)
+ break;
+ }
+
+ #else
+
+ MIIShiftOutPhyData(PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+ Command = ((PHY_TURNAROUND) |
+ (RegAddress << 2) |
+ (PhyAddress << 7) |
+ (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
+ Command <<= 16;
+ Command |= ((UINT32) Data);
+
+ MIIShiftOutPhyData(Command, 32);
+ #endif
+
+ return;
+ }
+
+ #if MACTYPE <= MAC_LIVENGOOD
+
+ STATIC UINT16 MIIShiftInPhyData(void)
+ {
+ UINT32 CtrlRegValue;
+ UINT16 Data = 0;
+ UINT8 i;
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+
+ CtrlRegValue &= ~E1000_CTRL_MDIO_DIR;
+ CtrlRegValue &= ~E1000_CTRL_MDIO;
+
+ E1000_WRITE_REG(Ctrl, CtrlRegValue);
+
+ RaiseMdcClock(&CtrlRegValue);
+ LowerMdcClock(&CtrlRegValue);
+
+ for (Data = 0, i = 0; i < 16; i++) {
+ Data = Data << 1;
+ RaiseMdcClock(&CtrlRegValue);
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+
+ if (CtrlRegValue & E1000_CTRL_MDIO)
+ Data |= 1;
+
+ LowerMdcClock(&CtrlRegValue);
+ }
+
+ RaiseMdcClock(&CtrlRegValue);
+ LowerMdcClock(&CtrlRegValue);
+
+ CtrlRegValue &= ~E1000_CTRL_MDIO;
+
+ return (Data);
+ }
+
+ STATIC
+ VOID
+ MIIShiftOutPhyData(IN UINT32 Data, IN UINT16 Count)
+ {
+ UINT32 CtrlRegValue;
+ UINT32 Mask;
+
+ if (Count > 32)
+ ASSERT(0);
+
+ Mask = 0x01;
+ Mask <<= (Count - 1);
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+
+ CtrlRegValue |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
+
+ while (Mask) {
+
+ if (Data & Mask)
+ CtrlRegValue |= E1000_CTRL_MDIO;
+ else
+ CtrlRegValue &= ~E1000_CTRL_MDIO;
+
+ E1000_WRITE_REG(Ctrl, CtrlRegValue);
+
+ DelayInMicroseconds(2);
+
+ RaiseMdcClock(&CtrlRegValue);
+ LowerMdcClock(&CtrlRegValue);
+
+ Mask = Mask >> 1;
+ }
+
+ CtrlRegValue &= ~E1000_CTRL_MDIO;
+ }
+
+ STATIC
+ VOID
+ RaiseMdcClock(IN OUT UINT32 * CtrlRegValue)
+ {
+
+ E1000_WRITE_REG(Ctrl, (*CtrlRegValue | E1000_CTRL_MDC));
+
+ DelayInMicroseconds(2);
+ }
+
+ STATIC
+ VOID
+ LowerMdcClock(IN OUT UINT32 * CtrlRegValue)
+ {
+
+ E1000_WRITE_REG(Ctrl, (*CtrlRegValue & ~E1000_CTRL_MDC));
+
+ DelayInMicroseconds(2);
+ }
+ #endif
+
+ VOID PhyHardwareReset()
+ {
+ UINT32 ExtCtrlRegValue, CtrlRegValue;
+
+ DEBUGFUNC("PhyHardwareReset")
+
+ DEBUGOUT("Resetting Phy...\n");
+
+ # if (MACTYPE > MAC_LIVENGOOD)
+
+ CtrlRegValue = E1000_READ_REG(Ctrl);
+
+ CtrlRegValue |= E1000_CTRL_PHY_RST;
+
+ E1000_WRITE_REG(Ctrl, CtrlRegValue);
+
+ DelayInMilliseconds(20);
+
+ CtrlRegValue &= ~E1000_CTRL_PHY_RST;
+
+ E1000_WRITE_REG(Ctrl, CtrlRegValue);
+
+ DelayInMilliseconds(20);
+ # else
+
+ ExtCtrlRegValue = E1000_READ_REG(Exct);
+
+ ExtCtrlRegValue |= E1000_CTRL_PHY_RESET_DIR4;
+
+ E1000_WRITE_REG(Exct, ExtCtrlRegValue);
+
+ DelayInMilliseconds(20);
+
+ ExtCtrlRegValue = E1000_READ_REG(Exct);
+
+ ExtCtrlRegValue &= ~E1000_CTRL_PHY_RESET4;
+
+ E1000_WRITE_REG(Exct, ExtCtrlRegValue);
+
+ DelayInMilliseconds(20);
+
+ ExtCtrlRegValue = E1000_READ_REG(Exct);
+
+ ExtCtrlRegValue |= E1000_CTRL_PHY_RESET4;
+
+ E1000_WRITE_REG(Exct, ExtCtrlRegValue);
+
+ DelayInMilliseconds(20);
+ #endif
+
+ return;
+ }
+ #if 0
+ BOOLEAN PhyReset(void)
+ {
+ UINT16 RegData;
+ UINT16 i;
+
+ DEBUGFUNC("PhyReset")
+
+ RegData = ReadPhyRegister(PHY_MII_CTRL_REG, PhyAddress);
+
+ RegData |= MII_CR_RESET;
+
+ WritePhyRegister(PHY_MII_CTRL_REG, PhyAddress, RegData);
+
+ i = 0;
+ while ((RegData & MII_CR_RESET) && i++ < 500) {
+ RegData = ReadPhyRegister(PHY_MII_CTRL_REG, PhyAddress);
+ DelayInMicroseconds(1);
+ }
+
+ if (i >= 500) {
+ DEBUGOUT("Timeout waiting for PHY to reset.\n");
+ return FALSE;
+ }
+
+ return TRUE;
+ }
+ #endif
+
+ BOOLEAN PhySetup(UINT32 DeviceControlReg)
+ {
+ UINT32 DeviceCtrlReg = 0;
+ UINT16 MiiCtrlReg, MiiStatusReg;
+ UINT16 MiiAutoNegAdvertiseReg, Mii1000TCtrlReg;
+ UINT16 i, Data;
+ UINT16 AutoNegHwSetting;
+ UINT16 AutoNegFCSetting;
+ BOOLEAN RestartAutoNeg = FALSE;
+ BOOLEAN ForceAutoNegRestart = FALSE;
+ DEBUGFUNC("PhySetup")
+
+ ASSERT(MacType >= MAC_LIVENGOOD);
+
+ if (MacType > MAC_WAINWRIGHT) {
+ DeviceControlReg |= (E1000_CTRL_ASDE | E1000_CTRL_SLU);
+ E1000_WRITE_REG(Ctrl, DeviceControlReg);
+ } else {
+ DeviceControlReg |= (E1000_CTRL_FRCSPD |
+ E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+ E1000_WRITE_REG(Ctrl, DeviceControlReg);
+
+ if (MacType == MAC_LIVENGOOD)
+ PhyHardwareReset();
+ }
+
+ PhyAddress = AutoDetectGigabitPhy();
+
+ if (PhyAddress > MAX_PHY_REG_ADDRESS) {
+
+ DEBUGOUT("PhySetup failure, did not detect valid phy.\n");
+ return (FALSE);
+ }
+
+ DEBUGOUT1("Phy ID = %x \n", PhyId);
+
+ MiiCtrlReg = ReadPhyRegister(PHY_MII_CTRL_REG, PhyAddress);
+
+ DEBUGOUT1("MII Ctrl Reg contents = %x\n", MiiCtrlReg);
+
+ if (!(MiiCtrlReg & MII_CR_AUTO_NEG_EN))
+ ForceAutoNegRestart = TRUE;
+
+ MiiCtrlReg &= ~(MII_CR_ISOLATE);
+
+ WritePhyRegister(PHY_MII_CTRL_REG, PhyAddress, MiiCtrlReg);
+
+ Data = ReadPhyRegister(PXN_PHY_SPEC_CTRL_REG, PhyAddress);
+
+ Data |= PXN_PSCR_ASSERT_CRS_ON_TX;
+
+ DEBUGOUT1("Paxson PSCR: %x \n", Data);
+
+ WritePhyRegister( PXN_PHY_SPEC_CTRL_REG, PhyAddress, Data);
+
+ Data = ReadPhyRegister(PXN_EXT_PHY_SPEC_CTRL_REG, PhyAddress);
+
+ Data |= PXN_EPSCR_TX_CLK_25;
+
+ WritePhyRegister(PXN_EXT_PHY_SPEC_CTRL_REG, PhyAddress, Data);
+
+ MiiAutoNegAdvertiseReg = ReadPhyRegister(PHY_AUTONEG_ADVERTISEMENT,
+ PhyAddress);
+
+ AutoNegHwSetting = (MiiAutoNegAdvertiseReg >> 5) & 0xF;
+
+ Mii1000TCtrlReg = ReadPhyRegister(PHY_1000T_CTRL_REG,
+ PhyAddress);
+
+ AutoNegHwSetting |= ((Mii1000TCtrlReg & 0x0300) >> 4);
+
+ AutoNegFCSetting = ((MiiAutoNegAdvertiseReg & 0x0C00) >> 10);
+
+ AutoNegAdvertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+ if (AutoNegAdvertised == 0)
+ AutoNegAdvertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+ if (!ForceAutoNegRestart && AutoNeg &&
+ (AutoNegAdvertised == AutoNegHwSetting) &&
+ (FlowControl == AutoNegFCSetting)) {
+ DEBUGOUT("No overrides - Reading MII Status Reg..\n");
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ DEBUGOUT1("MII Status Reg contents = %x\n", MiiStatusReg);
+
+ if (MiiStatusReg & MII_SR_LINK_STATUS) {
+ Data = ReadPhyRegister(PXN_PHY_SPEC_STAT_REG,
+ PhyAddress);
+ DEBUGOUT1("Paxson Phy Specific Status Reg contents = %x\n",
+ Data);
+
+ #if (MACTYPE > MAC_WAINWRIGHT)
+ ConfigureCollisionDistance();
+ #else
+ ConfigureMacToPhySettings(Data);
+ #endif
+ #ifdef USE_COMPLEX_VERSION
+ ConfigFlowControlAfterLinkUp();
+ #endif
+ return (TRUE);
+ }
+ }
+
+ if (AutoNeg) {
+ DEBUGOUT
+ ("Livengood - Reconfiguring auto-neg advertisement params\n");
+ RestartAutoNeg = PhySetupAutoNegAdvertisement();
+ } else {
+ DEBUGOUT("Livengood - Forcing speed and duplex\n");
+ // PhyForceSpeedAndDuplex();
+ }
+
+ if (RestartAutoNeg) {
+ DEBUGOUT("Restarting Auto-Neg\n");
+
+ MiiCtrlReg = ReadPhyRegister(PHY_MII_CTRL_REG,
+ PhyAddress);
+
+ MiiCtrlReg |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
+
+ WritePhyRegister(PHY_MII_CTRL_REG,
+ PhyAddress, MiiCtrlReg);
+
+ if (WaitAutoNegComplete)
+ WaitForAutoNeg();
+
+ }
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ DEBUGOUT1("Checking for link status - MII Status Reg contents = %x\n",
+ MiiStatusReg);
+
+ for (i = 0; i < 10; i++) {
+ if (MiiStatusReg & MII_SR_LINK_STATUS) {
+ break;
+ }
+ DelayInMicroseconds(10);
+ DEBUGOUT(". ");
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+ }
+
+ if (MiiStatusReg & MII_SR_LINK_STATUS) {
+
+ Data = ReadPhyRegister(PXN_PHY_SPEC_STAT_REG, PhyAddress);
+
+ DEBUGOUT1("Paxson Phy Specific Status Reg contents = %x\n", Data);
+
+ # if (MACTYPE > MAC_WAINWRIGHT)
+ ConfigureCollisionDistance();
+ # else
+ ConfigureMacToPhySettings(Data);
+ #endif
+
+ #ifdef USE_COMPLEX_VERSION
+ ConfigFlowControlAfterLinkUp();
+ #endif
+ DEBUGOUT("Valid link established!!!\n");
+ } else {
+ DEBUGOUT("Unable to establish link!!!\n");
+ }
+
+ return (TRUE);
+ }
+
+ BOOLEAN PhySetupAutoNegAdvertisement(void)
+ {
+
+ #ifdef USE_COMPLEX_VERSION
+ UINT16 MiiAutoNegAdvertiseReg, Mii1000TCtrlReg;
+
+ DEBUGFUNC("PhySetupAutoNegAdvertisement")
+
+ MiiAutoNegAdvertiseReg = ReadPhyRegister(PHY_AUTONEG_ADVERTISEMENT,
+ PhyAddress);
+
+ Mii1000TCtrlReg = ReadPhyRegister(PHY_1000T_CTRL_REG,
+ PhyAddress);
+
+ MiiAutoNegAdvertiseReg &= ~REG4_SPEED_MASK;
+ Mii1000TCtrlReg &= ~REG9_SPEED_MASK;
+
+ DEBUGOUT2("AutoNegAdvertised %x %x\n", AutoNegAdvertised,PhyAddress);
+
+ if (AutoNegAdvertised & ADVERTISE_10_HALF) {
+ DEBUGOUT("Advertise 10mb Half duplex\n");
+ MiiAutoNegAdvertiseReg |= NWAY_AR_10T_HD_CAPS;
+ }
+
+ if (AutoNegAdvertised & ADVERTISE_10_FULL) {
+ DEBUGOUT("Advertise 10mb Full duplex\n");
+ MiiAutoNegAdvertiseReg |= NWAY_AR_10T_FD_CAPS;
+ }
+
+ if (AutoNegAdvertised & ADVERTISE_100_HALF) {
+ DEBUGOUT("Advertise 100mb Half duplex\n");
+ MiiAutoNegAdvertiseReg |= NWAY_AR_100TX_HD_CAPS;
+ }
+
+ if (AutoNegAdvertised & ADVERTISE_100_FULL) {
+ DEBUGOUT("Advertise 100mb Full duplex\n");
+ MiiAutoNegAdvertiseReg |= NWAY_AR_100TX_FD_CAPS;
+ }
+
+ if (AutoNegAdvertised & ADVERTISE_1000_HALF) {
+ DEBUGOUT
+ ("Advertise 1000mb Half duplex requested, request denied!\n");
+ }
+
+ if (AutoNegAdvertised & ADVERTISE_1000_FULL) {
+ DEBUGOUT("Advertise 1000mb Full duplex\n");
+ Mii1000TCtrlReg |= CR_1000T_FD_CAPS;
+ }
+
+ switch (FlowControl) {
+ case FLOW_CONTROL_NONE:
+
+ MiiAutoNegAdvertiseReg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+
+ break;
+
+ case FLOW_CONTROL_RECEIVE_PAUSE:
+
+ MiiAutoNegAdvertiseReg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+
+ break;
+
+ case FLOW_CONTROL_TRANSMIT_PAUSE:
+
+ MiiAutoNegAdvertiseReg |= NWAY_AR_ASM_DIR;
+ MiiAutoNegAdvertiseReg &= ~NWAY_AR_PAUSE;
+
+ break;
+
+ case FLOW_CONTROL_FULL:
+
+ MiiAutoNegAdvertiseReg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+
+ break;
+
+ default:
+
+ DEBUGOUT("Flow control param set incorrectly\n");
+ ASSERT(0);
+ break;
+ }
+
+ WritePhyRegister(PHY_AUTONEG_ADVERTISEMENT,
+ PhyAddress, MiiAutoNegAdvertiseReg);
+
+ DEBUGOUT1("Auto-Neg Advertising %x\n", MiiAutoNegAdvertiseReg);
+
+ WritePhyRegister(PHY_1000T_CTRL_REG,
+ PhyAddress, Mii1000TCtrlReg);
+ #else
+ UINT16 Mii1000TCtrlReg;
+ Mii1000TCtrlReg = ReadPhyRegister(PHY_1000T_CTRL_REG,
+ PhyAddress);
+ Mii1000TCtrlReg &= ~REG9_SPEED_MASK;
+ Mii1000TCtrlReg |= CR_1000T_FD_CAPS;
+ WritePhyRegister(PHY_AUTONEG_ADVERTISEMENT,
+ PhyAddress, 0x1e1);
+ #endif
+ return (TRUE);
+ }
+ #if 0
+ STATIC VOID PhyForceSpeedAndDuplex(void)
+ {
+ UINT16 MiiCtrlReg;
+ UINT16 MiiStatusReg;
+ UINT16 PhyData;
+ UINT16 i;
+ UINT32 TctlReg;
+ UINT32 DeviceCtrlReg;
+ UINT32 Shift32;
+
+ DEBUGFUNC("PhyForceSpeedAndDuplex")
+
+ FlowControl = FLOW_CONTROL_NONE;
+
+ DEBUGOUT1("FlowControl = %d\n", FlowControl);
+
+ DeviceCtrlReg = E1000_READ_REG(Ctrl);
+
+ DeviceCtrlReg |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+ DeviceCtrlReg &= ~(DEVICE_SPEED_MASK);
+
+ DeviceCtrlReg &= ~E1000_CTRL_ASDE;
+
+ MiiCtrlReg = ReadPhyRegister(PHY_MII_CTRL_REG, PhyAddress);
+
+ MiiCtrlReg &= ~MII_CR_AUTO_NEG_EN;
+
+ if (Adapter->ForcedSpeedDuplex == FULL_100 ||
+ Adapter->ForcedSpeedDuplex == FULL_10) {
+
+ DeviceCtrlReg |= E1000_CTRL_FD;
+ MiiCtrlReg |= MII_CR_FULL_DUPLEX;
+
+ DEBUGOUT("Full Duplex\n");
+ } else {
+
+ DeviceCtrlReg &= ~E1000_CTRL_FD;
+ MiiCtrlReg &= ~MII_CR_FULL_DUPLEX;
+
+ DEBUGOUT("Half Duplex\n");
+ }
+
+ if (Adapter->ForcedSpeedDuplex == FULL_100 ||
+ Adapter->ForcedSpeedDuplex == HALF_100) {
+
+ DeviceCtrlReg |= E1000_CTRL_SPD_100;
+ MiiCtrlReg |= MII_CR_SPEED_100;
+ MiiCtrlReg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
+
+ DEBUGOUT("Forcing 100mb ");
+ } else {
+
+ DeviceCtrlReg &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+ MiiCtrlReg |= MII_CR_SPEED_10;
+ MiiCtrlReg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
+
+ DEBUGOUT("Forcing 10mb ");
+ }
+
+ TctlReg = E1000_READ_REG(Tctl);
+ DEBUGOUT1("TctlReg = %x\n", TctlReg);
+
+ if (!(MiiCtrlReg & MII_CR_FULL_DUPLEX)) {
+
+ TctlReg &= ~E1000_TCTL_COLD;
+ Shift32 = E1000_HDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ } else {
+
+ TctlReg &= ~E1000_TCTL_COLD;
+ Shift32 = E1000_FDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ }
+
+ E1000_WRITE_REG(Tctl, TctlReg);
+
+ E1000_WRITE_REG(Ctrl, DeviceCtrlReg);
+
+ PhyData = ReadPhyRegister(PXN_PHY_SPEC_CTRL_REG, PhyAddress);
+
+ PhyData &= ~PXN_PSCR_AUTO_X_MODE;
+
+ WritePhyRegister(PXN_PHY_SPEC_CTRL_REG, PhyAddress, PhyData);
+
+ DEBUGOUT1("Paxson PSCR: %x \n", PhyData);
+
+ MiiCtrlReg |= MII_CR_RESET;
+
+ WritePhyRegister(PHY_MII_CTRL_REG, PhyAddress, MiiCtrlReg);
+
+ if (Adapter->WaitAutoNegComplete) {
+
+ DEBUGOUT("Waiting for forced speed/duplex link.\n");
+ MiiStatusReg = 0;
+
+ #define PHY_WAIT_FOR_FORCED_TIME 20
+
+ for (i = 20; i > 0; i--) {
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ if (MiiStatusReg & MII_SR_LINK_STATUS) {
+ break;
+ }
+ DelayInMilliseconds(100);
+ }
+
+ if (i == 0) {
+
+ PxnPhyResetDsp();
+ }
+
+ for (i = 20; i > 0; i--) {
+ if (MiiStatusReg & MII_SR_LINK_STATUS) {
+ break;
+ }
+
+ DelayInMilliseconds(100);
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ }
+ }
+
+ PhyData = ReadPhyRegister(PXN_EXT_PHY_SPEC_CTRL_REG,
+ PhyAddress);
+
+ PhyData |= PXN_EPSCR_TX_CLK_25;
+
+ WritePhyRegister(PXN_EXT_PHY_SPEC_CTRL_REG,
+ PhyAddress, PhyData);
+
+ PhyData = ReadPhyRegister(PXN_PHY_SPEC_CTRL_REG, PhyAddress);
+
+ PhyData |= PXN_PSCR_ASSERT_CRS_ON_TX;
+
+ WritePhyRegister(PXN_PHY_SPEC_CTRL_REG, PhyAddress, PhyData);
+ DEBUGOUT1("After force, Paxson Phy Specific Ctrl Reg = %4x\r\n",
+ PhyData);
+
+ return;
+ }
+ #endif
+
+ VOID
+ ConfigureMacToPhySettings(IN UINT16 MiiRegisterData)
+ {
+ UINT32 DeviceCtrlReg, TctlReg;
+ UINT32 Shift32;
+
+ DEBUGFUNC("ConfigureMacToPhySettings")
+
+ TctlReg = E1000_READ_REG(Tctl);
+ DEBUGOUT1("TctlReg = %x\n", TctlReg);
+
+ DeviceCtrlReg = E1000_READ_REG(Ctrl);
+
+ DeviceCtrlReg |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+ DeviceCtrlReg &= ~(DEVICE_SPEED_MASK);
+
+ DEBUGOUT1("MII Register Data = %x\r\n", MiiRegisterData);
+
+ DeviceCtrlReg &= ~E1000_CTRL_ILOS;
+
+ if (MiiRegisterData & PXN_PSSR_DPLX) {
+ DeviceCtrlReg |= E1000_CTRL_FD;
+
+ TctlReg &= ~E1000_TCTL_COLD;
+ Shift32 = E1000_FDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ } else {
+ DeviceCtrlReg &= ~E1000_CTRL_FD;
+
+ if ((MiiRegisterData & PXN_PSSR_SPEED) == PXN_PSSR_1000MBS) {
+ TctlReg &= ~E1000_TCTL_COLD;
+ Shift32 = E1000_GB_HDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+
+ TctlReg |= E1000_TCTL_PBE;
+
+ } else {
+ TctlReg &= ~E1000_TCTL_COLD;
+ Shift32 = E1000_HDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ }
+ }
+
+ if ((MiiRegisterData & PXN_PSSR_SPEED) == PXN_PSSR_1000MBS)
+ DeviceCtrlReg |= E1000_CTRL_SPD_1000;
+ else if ((MiiRegisterData & PXN_PSSR_SPEED) == PXN_PSSR_100MBS)
+ DeviceCtrlReg |= E1000_CTRL_SPD_100;
+ else
+ DeviceCtrlReg &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+
+ E1000_WRITE_REG(Tctl, TctlReg);
+
+ E1000_WRITE_REG(Ctrl, DeviceCtrlReg);
+
+ return;
+ }
+
+ VOID ConfigureCollisionDistance(void)
+ {
+
+ #ifdef USE_COMPLEX_VERSION
+ UINT32 TctlReg;
+ UINT16 Speed;
+ UINT16 Duplex;
+ UINT32 Shift32;
+
+ DEBUGFUNC("ConfigureCollisionDistance")
+
+ GetSpeedAndDuplex(&Speed, &Duplex);
+
+ TctlReg = E1000_READ_REG(Tctl);
+ DEBUGOUT1("TctlReg = %x\n", TctlReg);
+
+ TctlReg &= ~E1000_TCTL_COLD;
+
+ if (Duplex == FULL_DUPLEX) {
+
+ Shift32 = E1000_FDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ } else {
+
+ if (Speed == SPEED_1000) {
+ Shift32 = E1000_GB_HDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+
+ TctlReg |= E1000_TCTL_PBE;
+
+ } else {
+ Shift32 = E1000_HDX_COLLISION_DISTANCE;
+ Shift32 <<= E1000_COLD_SHIFT;
+ TctlReg |= Shift32;
+ }
+ }
+
+ E1000_WRITE_REG(Tctl, TctlReg);
+ #endif
+
+ return;
+ }
+
+
+ UINT32 AutoDetectGigabitPhy(void)
+ {
+ UINT32 PhyAddress = 1;
+ UINT32 PhyIDHi;
+ UINT16 PhyIDLo;
+ BOOLEAN GotOne = FALSE;
+
+ DEBUGFUNC("AutoDetectGigabitPhy")
+
+ while ((!GotOne) && (PhyAddress <= MAX_PHY_REG_ADDRESS)) {
+
+ PhyIDHi = ReadPhyRegister(PHY_PHY_ID_REG1, PhyAddress);
+
+ DelayInMicroseconds(2);
+
+ PhyIDLo = ReadPhyRegister(PHY_PHY_ID_REG2, PhyAddress);
+
+ PhyId = (PhyIDLo | (PhyIDHi << 16)) & PHY_REVISION_MASK;
+
+ if (PhyId == PAXSON_PHY_88E1000 ||
+ PhyId == PAXSON_PHY_88E1000S ||
+ PhyId == PAXSON_PHY_INTEGRATED) {
+ DEBUGOUT2("PhyId 0x%x detected at address 0x%x\n",
+ PhyId, PhyAddress);
+
+ GotOne = TRUE;
+ } else {
+ PhyAddress++;
+ }
+
+ }
+
+ if (PhyAddress > MAX_PHY_REG_ADDRESS) {
+ DEBUGOUT("Could not auto-detect Phy!\n");
+ }
+
+ return (PhyAddress);
+ }
+
+ VOID PxnPhyResetDsp(void)
+ {
+ WritePhyRegister( 29, PhyAddress, 0x1d);
+ WritePhyRegister( 30, PhyAddress, 0xc1);
+ WritePhyRegister( 30, PhyAddress, 0x00);
+ }
+
+ BOOLEAN WaitForAutoNeg(void)
+ {
+ BOOLEAN AutoNegComplete = FALSE;
+ UINT16 i;
+ UINT16 MiiStatusReg;
+
+ DEBUGFUNC("WaitForAutoNeg");
+
+ DEBUGOUT("Waiting for Auto-Neg to complete.\n");
+ MiiStatusReg = 0;
+
+ for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+
+ MiiStatusReg = ReadPhyRegister(PHY_MII_STATUS_REG,
+ PhyAddress);
+
+ if (MiiStatusReg & MII_SR_AUTONEG_COMPLETE) {
+ AutoNegComplete = TRUE;
+ break;
+ }
+
+ DelayInMilliseconds(100);
+ }
+
+ return (AutoNegComplete);
+ }
diff -rc2P -x '*~' grub-0.93/netboot/e1000_phy.h
grub-0.93-e1000/netboot/e1000_phy.h
*** grub-0.93/netboot/e1000_phy.h 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/e1000_phy.h 2003-03-14 12:21:42.000000000 +0000
***************
*** 0 ****
--- 1,319 ----
+ /*****************************************************************************
+ *****************************************************************************
+
+ Copyright (c) 1999 - 2001, Intel Corporation
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the
documentation
+ and/or other materials provided with the distribution.
+
+ 3. Neither the name of Intel Corporation nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ *****************************************************************************
+
*****************************************************************************/
+
+ /* Workfile: phy.h */
+ /* Revision: 6 */
+ /* Date: 3/07/01 3:55p */
+
+ #ifndef _PHY_
+ #define _PHY_
+ #include "e1000.h"
+
+ #define _PHY_
+
+ #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
+ #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
+ #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
+ #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
+ #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
+ #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
+ #define E1000_CTRL_PHY_RESET_DIR4 E1000_EXCTRL_SWDPIO4
+ #define E1000_CTRL_PHY_RESET4 E1000_EXCTRL_SWDPIN4
+
+ #define PHY_MII_CTRL_REG 0x00
+ #define PHY_MII_STATUS_REG 0x01
+ #define PHY_PHY_ID_REG1 0x02
+ #define PHY_PHY_ID_REG2 0x03
+ #define PHY_AUTONEG_ADVERTISEMENT 0x04
+ #define PHY_AUTONEG_LP_BPA 0x05
+ #define PHY_AUTONEG_EXPANSION_REG 0x06
+ #define PHY_AUTONEG_NEXT_PAGE_TX 0x07
+ #define PHY_AUTONEG_LP_RX_NEXT_PAGE 0x08
+ #define PHY_1000T_CTRL_REG 0x09
+ #define PHY_1000T_STATUS_REG 0x0A
+ #define PHY_IEEE_EXT_STATUS_REG 0x0F
+
+ #define PXN_PHY_SPEC_CTRL_REG 0x10
+ #define PXN_PHY_SPEC_STAT_REG 0x11
+ #define PXN_INT_ENABLE_REG 0x12
+ #define PXN_INT_STATUS_REG 0x13
+ #define PXN_EXT_PHY_SPEC_CTRL_REG 0x14
+ #define PXN_RX_ERROR_COUNTER 0x15
+ #define PXN_LED_CTRL_REG 0x18
+
+ #define MAX_PHY_REG_ADDRESS 0x1F
+
+ #define MII_CR_SPEED_SELECT_MSB 0x0040
+ #define MII_CR_COLL_TEST_ENABLE 0x0080
+ #define MII_CR_FULL_DUPLEX 0x0100
+ #define MII_CR_RESTART_AUTO_NEG 0x0200
+ #define MII_CR_ISOLATE 0x0400
+ #define MII_CR_POWER_DOWN 0x0800
+ #define MII_CR_AUTO_NEG_EN 0x1000
+ #define MII_CR_SPEED_SELECT_LSB 0x2000
+ #define MII_CR_LOOPBACK 0x4000
+ #define MII_CR_RESET 0x8000
+
+ #define MII_SR_EXTENDED_CAPS 0x0001
+ #define MII_SR_JABBER_DETECT 0x0002
+ #define MII_SR_LINK_STATUS 0x0004
+ #define MII_SR_AUTONEG_CAPS 0x0008
+ #define MII_SR_REMOTE_FAULT 0x0010
+ #define MII_SR_AUTONEG_COMPLETE 0x0020
+ #define MII_SR_PREAMBLE_SUPPRESS 0x0040
+ #define MII_SR_EXTENDED_STATUS 0x0100
+ #define MII_SR_100T2_HD_CAPS 0x0200
+ #define MII_SR_100T2_FD_CAPS 0x0400
+ #define MII_SR_10T_HD_CAPS 0x0800
+ #define MII_SR_10T_FD_CAPS 0x1000
+ #define MII_SR_100X_HD_CAPS 0x2000
+ #define MII_SR_100X_FD_CAPS 0x4000
+ #define MII_SR_100T4_CAPS 0x8000
+
+ #define NWAY_AR_SELECTOR_FIELD 0x0001
+ #define NWAY_AR_10T_HD_CAPS 0x0020
+ #define NWAY_AR_10T_FD_CAPS 0x0040
+ #define NWAY_AR_100TX_HD_CAPS 0x0080
+ #define NWAY_AR_100TX_FD_CAPS 0x0100
+ #define NWAY_AR_100T4_CAPS 0x0200
+ #define NWAY_AR_PAUSE 0x0400
+ #define NWAY_AR_ASM_DIR 0x0800
+ #define NWAY_AR_REMOTE_FAULT 0x2000
+ #define NWAY_AR_NEXT_PAGE 0x8000
+
+ #define NWAY_LPAR_SELECTOR_FIELD 0x0000
+ #define NWAY_LPAR_10T_HD_CAPS 0x0020
+ #define NWAY_LPAR_10T_FD_CAPS 0x0040
+ #define NWAY_LPAR_100TX_HD_CAPS 0x0080
+ #define NWAY_LPAR_100TX_FD_CAPS 0x0100
+ #define NWAY_LPAR_100T4_CAPS 0x0200
+ #define NWAY_LPAR_PAUSE 0x0400
+ #define NWAY_LPAR_ASM_DIR 0x0800
+ #define NWAY_LPAR_REMOTE_FAULT 0x2000
+ #define NWAY_LPAR_ACKNOWLEDGE 0x4000
+ #define NWAY_LPAR_NEXT_PAGE 0x8000
+
+ #define NWAY_ER_LP_NWAY_CAPS 0x0001
+ #define NWAY_ER_PAGE_RXD 0x0002
+ #define NWAY_ER_NEXT_PAGE_CAPS 0x0004
+ #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008
+ #define NWAY_ER_PAR_DETECT_FAULT 0x0100
+
+ #define NPTX_MSG_CODE_FIELD 0x0001
+ #define NPTX_TOGGLE 0x0800
+
+ #define NPTX_ACKNOWLDGE2 0x1000
+
+ #define NPTX_MSG_PAGE 0x2000
+ #define NPTX_NEXT_PAGE 0x8000
+
+ #define LP_RNPR_MSG_CODE_FIELD 0x0001
+ #define LP_RNPR_TOGGLE 0x0800
+
+ #define LP_RNPR_ACKNOWLDGE2 0x1000
+
+ #define LP_RNPR_MSG_PAGE 0x2000
+ #define LP_RNPR_ACKNOWLDGE 0x4000
+ #define LP_RNPR_NEXT_PAGE 0x8000
+
+ #define CR_1000T_ASYM_PAUSE 0x0080
+ #define CR_1000T_HD_CAPS 0x0100
+
+ #define CR_1000T_FD_CAPS 0x0200
+
+ #define CR_1000T_REPEATER_DTE 0x0400
+
+ #define CR_1000T_MS_VALUE 0x0800
+
+ #define CR_1000T_MS_ENABLE 0x1000
+
+ #define CR_1000T_TEST_MODE_NORMAL 0x0000
+ #define CR_1000T_TEST_MODE_1 0x2000
+ #define CR_1000T_TEST_MODE_2 0x4000
+ #define CR_1000T_TEST_MODE_3 0x6000
+ #define CR_1000T_TEST_MODE_4 0x8000
+
+ #define SR_1000T_IDLE_ERROR_CNT 0x0000
+ #define SR_1000T_ASYM_PAUSE_DIR 0x0100
+ #define SR_1000T_LP_HD_CAPS 0x0400
+
+ #define SR_1000T_LP_FD_CAPS 0x0800
+
+ #define SR_1000T_REMOTE_RX_STATUS 0x1000
+ #define SR_1000T_LOCAL_RX_STATUS 0x2000
+ #define SR_1000T_MS_CONFIG_RES 0x4000
+ #define SR_1000T_MS_CONFIG_FAULT 0x8000
+
+ #define IEEE_ESR_1000T_HD_CAPS 0x1000
+
+ #define IEEE_ESR_1000T_FD_CAPS 0x2000
+
+ #define IEEE_ESR_1000X_HD_CAPS 0x4000
+
+ #define IEEE_ESR_1000X_FD_CAPS 0x8000
+
+ #define PHY_TX_POLARITY_MASK 0x0100
+ #define PHY_TX_NORMAL_POLARITY 0
+
+ #define AUTO_POLARITY_DISABLE 0x0010
+
+ #define PXN_PSCR_JABBER_DISABLE 0x0001
+ #define PXN_PSCR_POLARITY_REVERSAL 0x0002
+ #define PXN_PSCR_SQE_TEST 0x0004
+ #define PXN_PSCR_INT_FIFO_DISABLE 0x0008
+
+ #define PXN_PSCR_CLK125_DISABLE 0x0010
+ #define PXN_PSCR_MDI_MANUAL_MODE 0x0000
+
+ #define PXN_PSCR_MDIX_MANUAL_MODE 0x0020
+ #define PXN_PSCR_AUTO_X_1000T 0x0040
+ #define PXN_PSCR_AUTO_X_MODE 0x0060
+ #define PXN_PSCR_10BT_EXT_DIST_ENABLE 0x0080
+ #define PXN_PSCR_MII_5BIT_ENABLE 0x0100
+ #define PXN_PSCR_SCRAMBLER_DISABLE 0x0200
+ #define PXN_PSCR_FORCE_LINK_GOOD 0x0400
+ #define PXN_PSCR_ASSERT_CRS_ON_TX 0x0800
+ #define PXN_PSCR_RX_FIFO_DEPTH_6 0x0000
+ #define PXN_PSCR_RX_FIFO_DEPTH_8 0x1000
+ #define PXN_PSCR_RX_FIFO_DEPTH_10 0x2000
+ #define PXN_PSCR_RX_FIFO_DEPTH_12 0x3000
+
+ #define PXN_PSCR_TXFR_FIFO_DEPTH_6 0x0000
+ #define PXN_PSCR_TXFR_FIFO_DEPTH_8 0x4000
+ #define PXN_PSCR_TXFR_FIFO_DEPTH_10 0x8000
+ #define PXN_PSCR_TXFR_FIFO_DEPTH_12 0xC000
+
+ #define PXN_PSSR_JABBER 0x0001
+ #define PXN_PSSR_REV_POLARITY 0x0002
+ #define PXN_PSSR_MDIX 0x0040
+ #define PXN_PSSR_LINK 0x0400
+ #define PXN_PSSR_SPD_DPLX_RESOLVED 0x0800
+ #define PXN_PSSR_PAGE_RCVD 0x1000
+ #define PXN_PSSR_DPLX 0x2000
+ #define PXN_PSSR_SPEED 0xC000
+ #define PXN_PSSR_10MBS 0x0000
+ #define PXN_PSSR_100MBS 0x4000
+ #define PXN_PSSR_1000MBS 0x8000
+
+ #define PXN_IER_JABBER 0x0001
+ #define PXN_IER_POLARITY_CHANGE 0x0002
+ #define PXN_IER_MDIX_CHANGE 0x0040
+ #define PXN_IER_FIFO_OVER_UNDERUN 0x0080
+ #define PXN_IER_FALSE_CARRIER 0x0100
+ #define PXN_IER_SYMBOL_ERROR 0x0200
+ #define PXN_IER_LINK_STAT_CHANGE 0x0400
+ #define PXN_IER_AUTO_NEG_COMPLETE 0x0800
+ #define PXN_IER_PAGE_RECEIVED 0x1000
+ #define PXN_IER_DUPLEX_CHANGED 0x2000
+ #define PXN_IER_SPEED_CHANGED 0x4000
+ #define PXN_IER_AUTO_NEG_ERR 0x8000
+
+ #define PXN_ISR_JABBER 0x0001
+ #define PXN_ISR_POLARITY_CHANGE 0x0002
+ #define PXN_ISR_MDIX_CHANGE 0x0040
+ #define PXN_ISR_FIFO_OVER_UNDERUN 0x0080
+ #define PXN_ISR_FALSE_CARRIER 0x0100
+ #define PXN_ISR_SYMBOL_ERROR 0x0200
+ #define PXN_ISR_LINK_STAT_CHANGE 0x0400
+ #define PXN_ISR_AUTO_NEG_COMPLETE 0x0800
+ #define PXN_ISR_PAGE_RECEIVED 0x1000
+ #define PXN_ISR_DUPLEX_CHANGED 0x2000
+ #define PXN_ISR_SPEED_CHANGED 0x4000
+ #define PXN_ISR_AUTO_NEG_ERR 0x8000
+
+ #define PXN_EPSCR_FIBER_LOOPBACK 0x4000
+ #define PXN_EPSCR_DOWN_NO_IDLE 0x8000
+
+ #define PXN_EPSCR_TX_CLK_2_5 0x0060
+ #define PXN_EPSCR_TX_CLK_25 0x0070
+ #define PXN_EPSCR_TX_CLK_0 0x0000
+
+ #define PXN_LCR_LED_TX 0x0001
+ #define PXN_LCR_LED_RX 0x0002
+ #define PXN_LCR_LED_DUPLEX 0x0004
+ #define PXN_LCR_LINK 0x0008
+ #define PXN_LCR_BLINK_RATE_42MS 0x0000
+ #define PXN_LCR_BLINK_RATE_84MS 0x0100
+ #define PXN_LCR_BLINK_RATE_170MS 0x0200
+ #define PXN_LCR_BLINK_RATE_340MS 0x0300
+ #define PXN_LCR_BLINK_RATE_670MS 0x0400
+
+ #define PXN_LCR_PULSE_STRETCH_OFF 0x0000
+ #define PXN_LCR_PULSE_STRETCH_21_42MS 0x1000
+ #define PXN_LCR_PULSE_STRETCH_42_84MS 0x2000
+ #define PXN_LCR_PULSE_STRETCH_84_170MS 0x3000
+ #define PXN_LCR_PULSE_STRETCH_170_340MS 0x4000
+ #define PXN_LCR_PULSE_STRETCH_340_670MS 0x5000
+ #define PXN_LCR_PULSE_STRETCH_670_13S 0x6000
+ #define PXN_LCR_PULSE_STRETCH_13_26S 0x7000
+
+ #define PHY_PREAMBLE 0xFFFFFFFF
+ #define PHY_SOF 0x01
+ #define PHY_OP_READ 0x02
+ #define PHY_OP_WRITE 0x01
+ #define PHY_TURNAROUND 0x02
+
+ #define PHY_PREAMBLE_SIZE 32
+
+ #define MII_CR_SPEED_1000 0x0040
+ #define MII_CR_SPEED_100 0x2000
+ #define MII_CR_SPEED_10 0x0000
+
+ #define E1000_PHY_ADDRESS 0x01
+ #define E1000_10MB_PHY_ADDRESS 0x02
+
+ #define PHY_AUTO_NEG_TIME 45
+
+ #define PAXSON_PHY_88E1000 0x01410C50
+ #define PAXSON_PHY_88E1000S 0x01410C40
+ #define PAXSON_PHY_INTEGRATED 0x01410C30
+
+ #define PHY_REVISION_MASK 0xFFFFFFF0
+ #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F
+
+ #define DEVICE_SPEED_MASK 0x00000300
+
+ #define REG4_SPEED_MASK 0x01E0
+ #define REG9_SPEED_MASK 0x0300
+
+ #define ADVERTISE_10_HALF 0x0001
+ #define ADVERTISE_10_FULL 0x0002
+ #define ADVERTISE_100_HALF 0x0004
+ #define ADVERTISE_100_FULL 0x0008
+ #define ADVERTISE_1000_HALF 0x0010
+ #define ADVERTISE_1000_FULL 0x0020
+
+ #endif /* _PHY_ */
+
diff -rc2P -x '*~' grub-0.93/netboot/Makefile.am
grub-0.93-e1000/netboot/Makefile.am
*** grub-0.93/netboot/Makefile.am 2002-01-02 21:56:40.000000000 +0000
--- grub-0.93-e1000/netboot/Makefile.am 2003-03-14 16:59:08.000000000 +0000
***************
*** 16,19 ****
--- 16,20 ----
EXTRA_libdrivers_a_SOURCES = 3c509.c 3c509.h 3c595.c 3c595.h 3c90x.c \
cs89x0.c cs89x0.h davicom.c depca.c eepro.c eepro100.c \
+ e1000.c e1000_fxhw.c e1000_phy.c \
epic100.c epic100.h fa311.c i82586.c lance.c natsemi.c \
ni5010.c ns8390.c ns8390.h otulip.c otulip.h rtl8139.c \
***************
*** 40,43 ****
--- 41,45 ----
eepro_drivers = eepro.o
eepro100_drivers = eepro100.o
+ e1000_drivers = e1000.o
epic100_drivers = epic100.o
#fa311_drivers = fa311.o
***************
*** 99,102 ****
--- 101,109 ----
$(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+ $(e1000_drivers): e1000.c e1000_phy.c e1000_fxhw.c e1000.h
+ $(e1000_drivers): %.o: e1000.c e1000_phy.c e1000_fxhw.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
$(epic100_drivers): epic100.c epic100.h
$(epic100_drivers): %.o: epic100.c
***************
*** 195,198 ****
--- 202,206 ----
eepro100_o_CFLAGS = -DINCLUDE_EEPRO100=1
epic100_o_CFLAGS = -DINCLUDE_EPIC100=1
+ e1000_o_CFLAGS = -DINCLUDE_E1000=1 -DMACTYPE=MAC_CORDOVA
#fa311_o_CFLAGS = -DINCLUDE_FA311=1
3c507_o_CFLAGS = -DINCLUDE_3C507=1
diff -rc2P -x '*~' grub-0.93/netboot/Makefile.in
grub-0.93-e1000/netboot/Makefile.in
*** grub-0.93/netboot/Makefile.in 2002-11-29 20:28:41.000000000 +0000
--- grub-0.93-e1000/netboot/Makefile.in 2003-03-14 16:59:34.000000000 +0000
***************
*** 103,106 ****
--- 103,107 ----
EXTRA_libdrivers_a_SOURCES = 3c509.c 3c509.h 3c595.c 3c595.h 3c90x.c \
cs89x0.c cs89x0.h davicom.c depca.c eepro.c eepro100.c \
+ e1000.c e1000_fxhw.c e1000_phy.c \
epic100.c epic100.h fa311.c i82586.c lance.c natsemi.c \
ni5010.c ns8390.c ns8390.h otulip.c otulip.h rtl8139.c \
***************
*** 129,132 ****
--- 130,134 ----
eepro_drivers = eepro.o
eepro100_drivers = eepro100.o
+ e1000_drivers = e1000.o
epic100_drivers = epic100.o
#fa311_drivers = fa311.o
***************
*** 158,161 ****
--- 160,164 ----
eepro100_o_CFLAGS = -DINCLUDE_EEPRO100=1
epic100_o_CFLAGS = -DINCLUDE_EPIC100=1
+ e1000_o_CFLAGS = -DINCLUDE_E1000=1 -DMACTYPE=MAC_CORDOVA
#fa311_o_CFLAGS = -DINCLUDE_FA311=1
3c507_o_CFLAGS = -DINCLUDE_3C507=1
***************
*** 207,210 ****
--- 210,216 ----
@AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-davicom.Po \
@AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-depca.Po \
+ @AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-e1000.Po \
+ @AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-e1000_fxhw.Po \
+ @AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-e1000_phy.Po \
@AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-eepro.Po \
@AMDEP_TRUE@ $(DEPDIR)/libdrivers_a-eepro100.Po \
***************
*** 270,273 ****
--- 276,282 ----
libdrivers_a-eepro.$(OBJEXT): eepro.c
libdrivers_a-eepro100.$(OBJEXT): eepro100.c
+ libdrivers_a-e1000.$(OBJEXT): e1000.c
+ libdrivers_a-e1000_fxhw.$(OBJEXT): e1000_fxhw.c
+ libdrivers_a-e1000_phy.$(OBJEXT): e1000_phy.c
libdrivers_a-epic100.$(OBJEXT): epic100.c
libdrivers_a-fa311.$(OBJEXT): fa311.c
***************
*** 305,308 ****
--- 314,320 ----
@AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
@AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
+ @AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
+ @AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
+ @AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
@AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
@AMDEP_TRUE@@am__include@ @address@hidden(DEPDIR)/address@hidden@
***************
*** 513,516 ****
--- 525,564 ----
$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-eepro100.obj
`cygpath -w eepro100.c`
+ libdrivers_a-e1000.o: e1000.c
+ @AMDEP_TRUE@ source='e1000.c' object='libdrivers_a-e1000.o' libtool=no
@AMDEPBACKSLASH@
+ @AMDEP_TRUE@ depfile='$(DEPDIR)/libdrivers_a-e1000.Po'
tmpdepfile='$(DEPDIR)/libdrivers_a-e1000.TPo' @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-e1000.o `test
-f e1000.c || echo '$(srcdir)/'`e1000.c
+
+ libdrivers_a-e1000.obj: e1000.c
+ @AMDEP_TRUE@ source='e1000.c' object='libdrivers_a-e1000.obj' libtool=no
@AMDEPBACKSLASH@
+ @AMDEP_TRUE@ depfile='$(DEPDIR)/libdrivers_a-e1000.Po'
tmpdepfile='$(DEPDIR)/libdrivers_a-e1000.TPo' @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-e1000.obj
`cygpath -w e1000.c`
+
+ libdrivers_a-e1000_fxhw.o: e1000_fxhw.c
+ @AMDEP_TRUE@ source='e1000_fxhw.c' object='libdrivers_a-e1000_fxhw.o'
libtool=no @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ depfile='$(DEPDIR)/libdrivers_a-e1000_fxhw.Po'
tmpdepfile='$(DEPDIR)/libdrivers_a-e1000_fxhw.TPo' @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-e1000_fxhw.o
`test -f e1000_fxhw.c || echo '$(srcdir)/'`e1000_fxhw.c
+
+ libdrivers_a-e1000_fxhw.obj: e1000_fxhw.c
+ @AMDEP_TRUE@ source='e1000_fxhw.c' object='libdrivers_a-e1000_fxhw.obj'
libtool=no @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ depfile='$(DEPDIR)/libdrivers_a-e1000_fxhw.Po'
tmpdepfile='$(DEPDIR)/libdrivers_a-e1000_fxhw.TPo' @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-e1000_fxhw.obj
`cygpath -w e1000_fxhw.c`
+
+ libdrivers_a-e1000_phy.o: e1000_phy.c
+ @AMDEP_TRUE@ source='e1000_phy.c' object='libdrivers_a-e1000_phy.o'
libtool=no @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ depfile='$(DEPDIR)/libdrivers_a-e1000_phy.Po'
tmpdepfile='$(DEPDIR)/libdrivers_a-e1000_phy.TPo' @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-e1000_phy.o
`test -f e1000_phy.c || echo '$(srcdir)/'`e1000_phy.c
+
+ libdrivers_a-e1000_phy.obj: e1000_phy.c
+ @AMDEP_TRUE@ source='e1000_phy.c' object='libdrivers_a-e1000_phy.obj'
libtool=no @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ depfile='$(DEPDIR)/libdrivers_a-e1000_phy.Po'
tmpdepfile='$(DEPDIR)/libdrivers_a-e1000_phy.TPo' @AMDEPBACKSLASH@
+ @AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS)
$(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-e1000_phy.obj
`cygpath -w e1000_phy.c`
+
libdrivers_a-epic100.o: epic100.c
@AMDEP_TRUE@ source='epic100.c' object='libdrivers_a-epic100.o' libtool=no
@AMDEPBACKSLASH@
***************
*** 891,894 ****
--- 939,947 ----
$(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+ $(e1000_drivers): e1000.c e1000_phy.c e1000_fxhw.c e1000.h
+ $(e1000_drivers): %.o: e1000.c e1000_phy.c e1000_fxhw.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
$(epic100_drivers): epic100.c epic100.h
$(epic100_drivers): %.o: epic100.c
diff -rc2P -x '*~' grub-0.93/netboot/osdep.h grub-0.93-e1000/netboot/osdep.h
*** grub-0.93/netboot/osdep.h 2002-01-02 21:56:40.000000000 +0000
--- grub-0.93-e1000/netboot/osdep.h 2003-03-14 12:59:00.000000000 +0000
***************
*** 75,79 ****
--- 75,91 ----
#define swap16(x) __swap16(x)
+ #ifdef FREEBSD_PXEEMU
+ #undef htonl
+ #undef htons
+ #undef ntohl
+ #undef ntohs
+ #include <sys/types.h>
+ #include "/sys/boot/i386/libi386/pxe.h"
+ #include "/sys/boot/i386/btx/lib/btxv86.h"
+ #endif
+
+ //#include "linux-asm-string.h"
#include "linux-asm-io.h"
+ #include "stdint.h"
typedef unsigned long Address;
diff -rc2P -x '*~' grub-0.93/netboot/pci.h grub-0.93-e1000/netboot/pci.h
*** grub-0.93/netboot/pci.h 2002-01-02 21:56:40.000000000 +0000
--- grub-0.93-e1000/netboot/pci.h 2003-03-14 13:10:43.000000000 +0000
***************
*** 26,29 ****
--- 26,31 ----
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
+ #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special
cycles */
+ #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and
invalidate */
#define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
***************
*** 58,61 ****
--- 60,66 ----
#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
#endif
+ #ifndef PCI_BASE_ADDRESS_MEM_MASK
+ #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
+ #endif
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_ROM_ADDRESS 0x30 /* 32 bits */
***************
*** 130,139 ****
#define PCI_DEVICE_ID_INTEL_ID1029 0x1029
#define PCI_DEVICE_ID_INTEL_ID1030 0x1030
#define PCI_DEVICE_ID_INTEL_82562 0x2449
#define PCI_VENDOR_ID_AMD 0x1022
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_VENDOR_ID_AMD_HOMEPNA 0x1022
#define PCI_DEVICE_ID_AMD_HOMEPNA 0x2001
! #define PCI_VENDOR_ID_SMC_1211 0x1113
#define PCI_DEVICE_ID_SMC_1211 0x1211
#define PCI_VENDOR_ID_DEC 0x1011
--- 135,151 ----
#define PCI_DEVICE_ID_INTEL_ID1029 0x1029
#define PCI_DEVICE_ID_INTEL_ID1030 0x1030
+ #define PCI_DEVICE_ID_INTEL_ID1038 0x1038
#define PCI_DEVICE_ID_INTEL_82562 0x2449
+ #define PCI_DEVICE_ID_INTEL_82542 0x1000
+ #define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
+ #define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
+ #define PCI_DEVICE_ID_INTEL_82544EI_COPPER 0x1008
+ #define PCI_DEVICE_ID_INTEL_82544GC_CREB 0x100D
#define PCI_VENDOR_ID_AMD 0x1022
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_VENDOR_ID_AMD_HOMEPNA 0x1022
#define PCI_DEVICE_ID_AMD_HOMEPNA 0x2001
! #define PCI_VENDOR_ID_SMC_1211 0x1112
! #define PCI_VENDOR_ID_SMC_1211A 0x1113
#define PCI_DEVICE_ID_SMC_1211 0x1211
#define PCI_VENDOR_ID_DEC 0x1011
***************
*** 171,174 ****
--- 183,190 ----
#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021
+ #define PCI_VENDOR_ID_NETGEAR 0x1385
+ #define PCI_DEVICE_ID_NETGEAR_MA301 0x4100
+ #define PCI_VENDOR_ID_HARRIS 0x1260
+ #define PCI_DEVICE_ID_HARRIS_PRISM2 0x3873
struct pci_device {
diff -rc2P -x '*~' grub-0.93/netboot/stdint.h grub-0.93-e1000/netboot/stdint.h
*** grub-0.93/netboot/stdint.h 1970-01-01 01:00:00.000000000 +0100
--- grub-0.93-e1000/netboot/stdint.h 2003-03-14 12:58:15.000000000 +0000
***************
*** 0 ****
--- 1,14 ----
+ #ifndef STDINT_H
+ #define STDINT_H
+
+ typedef unsigned char uint8_t;
+ typedef unsigned short uint16_t;
+ typedef unsigned long uint32_t;
+ typedef unsigned long long uint64_t;
+
+ typedef signed char int8_t;
+ typedef signed short int16_t;
+ typedef signed long int32_t;
+ typedef signed long long int64_t;
+
+ #endif /* STDINT_H */
diff -rc2P -x '*~' grub-0.93/netboot/timer.c grub-0.93-e1000/netboot/timer.c
*** grub-0.93/netboot/timer.c 2002-01-02 21:56:40.000000000 +0000
--- grub-0.93-e1000/netboot/timer.c 2003-03-14 15:30:36.000000000 +0000
***************
*** 126,127 ****
--- 126,129 ----
#endif /* RTC_CURRTICKS */
+
+
- e1000 patch for grub 0.93,
James Scott <=