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[Bug-gnucap] shunt trouble

From: address@hidden
Subject: [Bug-gnucap] shunt trouble
Date: Thu, 30 Dec 2010 14:23:32 +0100
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv: Gecko/20100111 Thunderbird/3.0.1

Hello and Season's greetings

I tested it on different versions with cygwin on XP. One of them was gnucap-2009-11-10. It seems that gnucap doesn't simulate the whole circuit when I connect two logic gates with
a null voltage source in order to get sel=out1.

It was a big circuit but I took away all the gates that were not relevant to show what seems a bug. So I have just now out2 = AND(sel, NOT(sel)) with sel = out1, out1 = AND(in,in) and in = 0

out2 is not as expected : AND(sel=0, notsel=5) = 5 !

Here the Gnucap file
GnuCap File : circuit description
Vttl TTL 0 5
Vin in 0 0
UAND1 out1 0 TTL TTL in in cmos and
Vshunt sel out1 0
UINV notsel 0 TTL TTL sel cmos inv
UAND2 out2 0 TTL TTL notsel sel cmos and
.model cmos LOGIC (vmax=5)
.print tran + V(in)
.print tran + V(out1)
.print tran + V(sel)
.print tran + V(notsel)
.print tran + V(out2)

And the result for tran analysis:

#Time       V(in)      V(out1)    V(sel)     V(notsel)  V(out2)
 0.             0.           0.            0.            5.             5.
 100.E-6   0.           0.            0.            5.             5.

If I don't use Vshunt it works but what's the matter ?

And Al, thanks for all the job you have done.

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