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Re: [avr-libc-dev] XMega Watchdog clock domains not synchronized?

From: Bob Paddock
Subject: Re: [avr-libc-dev] XMega Watchdog clock domains not synchronized?
Date: Mon, 19 May 2014 12:58:16 -0400

On Mon, May 19, 2014 at 10:22 AM, Joerg Wunsch <address@hidden> wrote:
> As Bob Paddock wrote:
>> > I do not see where this clock domain synchronization is accounted for
>> > in avr/wdt.h wdt_enable().
> As *I* read it, this synchronization is something that happens
> internally to the device, and the SYNCBUSY bit only indicates
> whether a synchronization is still pending.

It is internal to the device, true.  Simply must wait for the slower
clock domain to catch up by stopping the faster domain, so that it is
no longer pending.

This is standard stuff anytime you cross clock domains.  Read just
about any RTC datasheet and it comes up.

> I wish the datasheet were a little more explicit here about what
> user code is expected to do with the SYNCBUSY bit.

I took it literally.  The clock domains must be synchronized to
communicate the enable/disable state between the different registers
(state machines?) of the part.

I do not remember from three years ago when I originally raised the
question, if waiting for SYNCBUSY fixed my random reset or not.  I
know I did implement it and it did not hurt.

Making a test case for something like this is almost impossible
because the drifting clock domains make it seem random, when they are
not synchronized.

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