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Re: [avr-libc-dev] correction in xmega wdt_enable/ wdt_enable

From: S, Pitchumani
Subject: Re: [avr-libc-dev] correction in xmega wdt_enable/ wdt_enable
Date: Wed, 14 May 2014 08:20:50 +0000

> -----Original Message-----
> From: Joerg Wunsch [mailto:address@hidden
> Sent: Wednesday, May 14, 2014 12:31 PM
> To: address@hidden
> Cc: S, Pitchumani
> Subject: Re: [avr-libc-dev] correction in xmega wdt_enable/ wdt_enable
> As S, Pitchumani wrote:
> > As per datasheet, wdt_enable should wait until SYNCBUSY bit in
> > STATUS register is cleared.
> I could not find a description that mandates this in the datasheet,
> but I think it makes sense.

Sorry, this is explained in xmega manual.

For example:
Xmega D manual - revision: 8210B-AVR-04/10
Section 9.7.1 explains CTRL register and how to set change enable and
WDT enable.

Section 9.7.3 explains STATUS register.

When writing to the CTRL or WINCTRL registers, the WDT needs to be 
synchronized to the other clock domains. During synchronization the 
SYNCBUSY bit will be read as one. This bit is automatically cleared after 
the synchronization is finished. Synchronization will only take place
when the ENABLE bit for the Watchdog Timer is set.

Other xmega manuals (A,B) also have same descriptions.

> > Please review and send your comments.
> Fine by me.



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