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[avr-libc-dev] Fix clock prescale set/get for mega16/32 hvb devices


From: Senthil Kumar Selvaraj
Subject: [avr-libc-dev] Fix clock prescale set/get for mega16/32 hvb devices
Date: Wed, 8 May 2013 16:20:45 +0530
User-agent: Mutt/1.5.21 (2010-09-15)

This patch re-implements clock_prescale_set/get for ATmega16/32 hvb 
(and hvbrevb) devices without making using the CLKPS2 and CLKPS3 macros, which 
are undefined for these devices.

Joerg okayed this patch (and a couple of others) a while back. Got lost
in the mists of time - recreated the patch against the latest trunk and 
sending it to the mailing list now.

Regards
Senthil

ChangeLog

2013-01-15  Pitchumani Sivanupandi  <address@hidden>

        * include/avr/power.h: Specialize clock_prescale_set/get
        for mega hvb devices


Index: include/avr/power.h
===================================================================
--- include/avr/power.h (revision 2395)
+++ include/avr/power.h (working copy)
@@ -1537,10 +1537,6 @@
 || defined(__AVR_ATmega3290__) \
 || defined(__AVR_ATmega3290A__) \
 || defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_ATmega32HVB__) \
-|| defined(__AVR_ATmega32HVBREVB__) \
-|| defined(__AVR_ATmega16HVB__) \
-|| defined(__AVR_ATmega16HVBREVB__) \
 || defined(__AVR_ATmega32M1__) \
 || defined(__AVR_ATmega32U2__) \
 || defined(__AVR_ATmega32U4__) \
@@ -1693,7 +1689,39 @@
 */
 #define clock_prescale_get()  (clock_div_t)(CLKPR & 
(uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
 
+#elif defined(__AVR_ATmega16HVB__) \
+|| defined(__AVR_ATmega16HVBREVB__) \
+|| defined(__AVR_ATmega32HVB__) \
+|| defined(__AVR_ATmega32HVBREVB__)
 
+typedef enum
+{
+    clock_div_1 = 0,
+    clock_div_2 = 1,
+    clock_div_4 = 2,
+    clock_div_8 = 3
+} clock_div_t;
+
+static __inline__ void clock_prescale_set(clock_div_t) 
__attribute__((__always_inline__));
+
+void clock_prescale_set(clock_div_t __x)
+{
+    uint8_t __tmp = _BV(CLKPCE);
+    __asm__ __volatile__ (
+        "in __tmp_reg__,__SREG__" "\n\t"
+        "cli" "\n\t"
+        "sts %1, %0" "\n\t"
+        "sts %1, %2" "\n\t"
+        "out __SREG__, __tmp_reg__"
+        : /* no outputs */
+        : "d" (__tmp),
+          "M" (_SFR_MEM_ADDR(CLKPR)),
+          "d" (__x)
+        : "r0");
+}
+
+#define clock_prescale_get()  (clock_div_t)(CLKPR & 
(uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
+
 #elif defined(__AVR_ATtiny24__) \
 || defined(__AVR_ATtiny24A__) \
 || defined(__AVR_ATtiny44__) \



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