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Re: [avr-gcc-list] Re: [avr-libc-dev] [bug #29774] prologue/epilogue sta
Re: [avr-gcc-list] Re: [avr-libc-dev] [bug #29774] prologue/epilogue stack pointer manipulation not interrupt safe in XMega
Sat, 12 Feb 2011 17:03:29 MST
Ruud Vlaming <address@hidden> said:
> On Tuesday 08 June 2010, Matthew wrote:
> > So here's what I have found so far. When executing SEI, one more
> > instruction can execute before the first interrupt is serviced. When
> > enabling interrupts by restoring the status register, interrupts can
> > occur immediately. When writing to SPL, interrupts are automatically
> > disabled until the next memory write (up to 4 cycles).
> Interesting info!
> Can you provide the sources for that or did you test it yourself?
> And do these statements hold for xmega en mega alike?
> > Therefore, the prologue and epilogue do not need to disable interrupts
> > at all. A write to SPL followed by a write to SPH should be interrupt
> > safe. I have not tested this yet.
> This seems hard to test, but is also very interesting.
The info about writing to SPL disabling interrupts is in the XMega A Manual
(doc8077.pdf) at the bottom of section 3.8. Note that the interrupt
architecture is NOT the same in the mega series.
The test case is quite simple with a JTAGICE. Set up an interrupt that is
always pending. The code will execute one opcode at a time between interrupts.
A breakpoint can be set at the line in the disassembly that you want to test
(such as restoring status register). Once at that point set a breakpoint
inside the interrupt and at the line after the opcode being tested. Getting
the interrupt first indicates that interrupts are not disabled.