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[avr-libc-dev] [bug #26734] Unsafe SP register changes in ISR_NOBLOCK in


From: Anatoly Sokolov
Subject: [avr-libc-dev] [bug #26734] Unsafe SP register changes in ISR_NOBLOCK interrupt handlers
Date: Wed, 03 Jun 2009 02:10:17 +0000
User-agent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; MRA 5.0 (build 02094); SLCC1; .NET CLR 2.0.50727; Media Center PC 5.0; .NET CLR 3.5.21022; .NET CLR 3.5.30729; .NET CLR 3.0.30618)

URL:
  <http://savannah.nongnu.org/bugs/?26734>

                 Summary: Unsafe SP register changes in ISR_NOBLOCK interrupt
handlers
                 Project: AVR C Runtime Library
            Submitted by: aesok
            Submitted on: Срд 03 Июн 2009 06:10:16
                Category: Library
                Severity: 5 - Blocker
                Priority: 5 - Normal
              Item Group: Header files
                  Status: None
        Percent Complete: 0%
             Assigned to: None
             Open/Closed: Open
         Discussion Lock: Any
                 Release: 1.6.6
           Fixed Release: None

    _______________________________________________________

Details:

Test case:
#include <avr/interrupt.h>
#include <compat/deprecated.h>

ISR(INT0_vect,ISR_NOBLOCK)
{
  volatile long long foo;
  
  foo = 1;
}

INTERRUPT(PCINT0_vect)
{
  volatile long long foo;
  
  foo = 1;
}

int main(void) 
{ 
  return 0;
}

For 'PCINT0_vect' interrupt handler correct code is generated:

INTERRUPT(PCINT0_vect)
{
  8c:   78 94           sei     // enable interrupt
....
  //  Correct. interrupt is disabled/enabled when SP register is changed
  9e:   cd b7           in      r28, 0x3d       ; 61
  a0:   de b7           in      r29, 0x3e       ; 62
  a2:   28 97           sbiw    r28, 0x08       ; 8
  a4:   f8 94           cli
  a6:   de bf           out     0x3e, r29       ; 62
  a8:   78 94           sei
  aa:   cd bf           out     0x3d, r28       ; 61

For 'INT0_vect' interrupt handler wrong code is generated:

ISR(INT0_vect,ISR_NOBLOCK)
{
  48:   78 94           sei     // enable interrupt
....
  //  WRONG! NO interrupt is disabled/enabled when SP register is changed
  5a:   cd b7           in      r28, 0x3d       ; 61
  5c:   de b7           in      r29, 0x3e       ; 62
  5e:   28 97           sbiw    r28, 0x08       ; 8
  60:   de bf           out     0x3e, r29       ; 62
  62:   cd bf           out     0x3d, r28       ; 61

Anatoly.




    _______________________________________________________

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