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RE: [avr-libc-dev] [RFC] Sleeping BOD API

From: Weddington, Eric
Subject: RE: [avr-libc-dev] [RFC] Sleeping BOD API
Date: Fri, 6 Feb 2009 15:46:14 -0700


> -----Original Message-----
> From: 
> address@hidden 
> [mailto:address@hidden
> org] On Behalf Of Joerg Wunsch
> Sent: Friday, February 06, 2009 3:27 PM
> To: address@hidden
> Subject: Re: [avr-libc-dev] [RFC] Sleeping BOD API
> As Weddington, Eric wrote:
> > Ok so the above works, but now a question about some theoretical
> > aspects of this. In practice, the MCUCR register is in the I/O
> > space, therefore it can be accessed with IN/OUT instructions. The
> > macro above works, but it *explicitly* specifies the OUT
> > instruction. But what if there were an AVR device where MCUCR were
> > *not* in the I/O space?
> I think you're hosed in that case anyway (depending on how the "within
> four clock cycles" restriction is to be interpreted).  Accessing the
> memory space takes two cycles per instruction, so IMHO you would want
> to have the to respective STS instructions back to back then, just to
> be on the safe side.  That means you'll need another temporary
> variable then, so you can preset both bit patterns in temp registers,
> and then fire the two STS instructions.
> The advantage (if you'd like to call it so :) of my suggested code
> snippet here is that it will fail assembly in case MCUCR is not in the
> OUT-accessible address space, while your code will compile but fail to
> work correctly (again, depending on hour the "four clock cycles" are
> measured).

This was supposed to be *theory*, but in repsonse to your question, if you read 
the datasheet:

"To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE 
must be set to
zero within four clock cycles. The BODS bit is active three clock cycles after 
it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. 
The BODS bit is
automatically cleared after three clock cycles."

So the timing is split into 2 steps.
- Within 4 cycles, set BODS and clear BODSE
- Withing 3 cycles, sleep.

So I believe the timing constraints could still be matched.

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