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Re: [avr-libc-dev] FAQ #27: "Why are interrupts re-enabled in the middle
Re: [avr-libc-dev] FAQ #27: "Why are interrupts re-enabled in the middle of writing the stack pointer?"
Tue, 22 May 2007 06:18:42 -0400
On Monday 21 May 2007 06:22, Schwichtenberg, Knut wrote:
> the official documentation of the Mega32 CPU (doc2503.pdf) - the one I'm
> using - says "When using the SEI instruction to enable interrupts, the
> instruction following SEI will be execued before any pending interrupts
Yes it does, as most of the data sheets today do.
What none of them say is that the same
"instruction following SEI will be executed before any pending interrupts"
type mechanism applies to other ways of setting the I-Bit
in SREG. This is a potential issue due to the way the stack is manipulated
in sections of avr-libc.
It seems fairly obvious that the part works the way we think
it works in FAQ #27, but I want to keep the liability lawyers
off my back if something bad ever would happen,
by doing proper due diligence in documenting things.
The fact that FAQ #27 even exists indicates that Atmel
has not documented this properly.
If I'm going to use a AVR in a new heart defibrillator, as an example
(if you watch any TV you've seen one of my products in a safety
application, can't get into the details here on the list),
then I want to make darn sure there is no ambiguities in how
the part works or the documentation for the part.