Re: [avr-libc-dev] [bug #14616] definition of sei() in interrupts.h is faulty

[Björn Haase]

Joerg Wunsch wrote on Montag, 26. September 2005 21:04 :
> GCC's documentation says:
>
>  The `volatile' keyword indicates that the instruction has important
> side-effects.  GCC will not delete a volatile `asm' if it is reachable.
> (The instruction can still be deleted if GCC can prove that
> control-flow will never reach the location of the instruction.)  In
> addition, GCC will not reschedule instructions across a volatile `asm'
> instruction.
>
> (Btw., I cannot find any documentation for the "memory" constraint.)
I've opened a bug report on

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24165

. Probably it's indeed a bug in gcc 4.0.0 that is already fixed in gcc 4.0.1 !

Here is the reduced test case:

/* Start of test case */

typedef unsigned char      uint8_t;
typedef unsigned short int uint16_t;

class class_with_volatile_data_structures
{
  public:

  void __attribute__ ((always_inline))
  wait_for_event (uint16_t event)
   {
     while (getval_protected () != event)
       ;
   };

  private:

  uint16_t
  getval_protected (void)
  {
    uint16_t result;

    asm volatile ("/* disable irq in cpu status */" : : );
    result = class_local_data;
    asm volatile ("/* enable irq */" : : );

    return result;
  }

  volatile uint16_t class_local_data;
};

class_with_volatile_data_structures object;

void
wait_for_42 (void)
{
  object.wait_for_event (42);
}

/* End of test case */


Compiler output reads for (buggy ?) avr-g++ (GCC) 4.0.0

_Z11wait_for_42v:
.L2:
/* #APP */
        /* disable irq in cpu status */
        /* enable irq */
/* #NOAPP */
        lds r24,object
        lds r25,(object)+1
        sbiw r24,42
        brne .L2
        ret

and for avr-g++ (GCC) 4.0.1 20050624 (prerelease)

_Z11wait_for_42v:
.L2:
/* #APP */
        /* disable irq in cpu status */
/* #NOAPP */
        lds r24,object
        lds r25,(object)+1
/* #APP */
        /* enable irq */
/* #NOAPP */
        sbiw r24,42
        brne .L2
        ret
.