[avr-libc-dev] IOCAN128.H Final(?) Changes

[Bruce Graham]

Ted,

Here is the patch and a fragment from the log file to move iocan128.h
from Rev 1.6 to Rev 1.7.
This should be the final set of changes.

Bruce

----------------------------
revision 1.7
date: 2004/05/21 00:11:42;  author: Bruce;  state: Exp;  lines: +6 -17
(1) Eliminate redundant PINA0 through PINA7 definitions.
(2) In comment, Change TCCR2 to TCCR2A
(3) In comment, Change SPIDR ro SPDR
(4) In Register MCUCR, Change bit name IVSE to IVSEL
(5) In Register CANBT2, Change bit number for SJW0 from 4 to 5
----------------------------

Index: iocan128/iocan128.h
===================================================================
RCS file: c:\src\master/iocan128/iocan128.h,v
retrieving revision 1.6
diff -u -r1.6 iocan128.h
--- iocan128/iocan128.h 20 May 2004 23:53:32 -0000      1.6
+++ iocan128/iocan128.h 20 May 2004 22:57:56 -0000
@@ -22,7 +22,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id: iocan128.h,v 1.6 2004/05/20 23:53:32 Bruce Exp $ */
+/* $Id: iocan128.h,v 1.6 2004/05/16 01:47:35 Bruce Exp $ */
 
 /* This file is based largely on:
    - iom128.h by Peter Jansen (bit defines)
@@ -56,17 +56,6 @@
 #define DDRA   _SFR_IO8(0x01)
 #define PORTA  _SFR_IO8(0x02)
 
-/* RegBits: PINA */
-#define PINA0                0
-#define PINA1                1
-#define PINA2                2
-#define PINA3                3
-#define PINA4                4
-#define PINA5                5
-#define PINA6                6
-#define PINA7                7
-/* EndRegBits */
-
 /* RegDef:  Port B */
 #define PINB   _SFR_IO8(0x03)
 #define DDRB   _SFR_IO8(0x04)
@@ -626,8 +615,8 @@
 #define    INTF0        0
 /* End Register Bits */
 
-/* Register Bits [TCCR2]  */
-/* Timer/Counter 2 Control Register - TCCR2 */
+/* Register Bits [TCCR2A]  */
+/* Timer/Counter 2 Control Register - TCCR2A */
 #define    FOC2A        7
 #define    WGM20        6
 #define    COM2A1       5
@@ -1255,7 +1244,7 @@
 /* End Register Bits */
 
 
-/* Register Bits [SPIDR]  */
+/* Register Bits [SPDR]  */
 /* SPI Data Register */
 #define    SPD7     7
 #define    SPD6     6
@@ -1288,7 +1277,7 @@
 /* MCU Control Register */
 #define    JTD     7
 #define    PUD     4
-#define    IVSE    1
+#define    IVSEL   1
 #define    IVCE    0
 /* End Register Bits */
 
@@ -1472,7 +1461,7 @@
 /* Register Bits [CANBT2]  */
 /* Bit Timing Register 2 */
 #define    SJW1       6
-#define    SJW0       4
+#define    SJW0       5
 #define    PRS2       3
 #define    PRS1       2
 #define    PRS0       1