[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [avr-libc-dev] A sugestion for avr-libc
From: |
Theodore A. Roth |
Subject: |
Re: [avr-libc-dev] A sugestion for avr-libc |
Date: |
Fri, 22 Aug 2003 12:03:12 -0700 (PDT) |
On Fri, 22 Aug 2003, Craig Rodgers wrote:
> First of all I'd like to thank the developers of avr-libc, you've done a
> fantastic job thus far.
>
> I haven't been using avr-libc for all that long now (about 2 months) but one
> of the more useful features that appears to be missing is the ability to
> assign and test individual bits in IO registers. Ie PA0=1; or if (DDRA == 1)
>
> Whilst some of this functionality is provided by current releases using the
> sbi, and cbi functions, I believe adding the capability to read and write
> bits without requiring the use of these instructions would enhance avr-libc.
>
> I have attached a cut down IO header (myIO.h) and a simple test program
> (main.c) that demonstrate how this functionality would be implemented into
> the current avr-libc and used in programs.
>
> I think you'll agree that it provides a much simpler means of accessing bits
> in the IO registers than the current mechanisms. This method of access also
> seems to be relatively common across other compilers/libraries I have come
> across (Mitsubishi M16C, some 8051 compilers etc).
>
> I have found avr-libc useful so if the general concessus is that this would
> be a useful addition I am happy enough to implement it. I would however like
> to make sure that I am not duplicating someone else's effort, if someone
> else out there is already working on this I would like to offer them my
> assistance.
I don't think that you gain anything by doing this except making the
include files more complicated.
The SBI insn is 2 clock cycles, and the LDI + OUT that gcc generates
is 2 cycles (1 each insn). See the instruction set data sheet for more
info on how many clock cycles each instruction uses.
As soon as you want to set more than 1 bit, using SBI becomes more
expensive (it's a wash when setting 1 bit).
As for testing bits, the following are equivalent:
/* MY_PORTA is a bit field structure. */
while (MY_PORTA.B0 == 0);
e0: d8 9b sbis 0x1b, 0 ; 27
e2: fe cf rjmp .-4 ; 0xe0
loop_until_bit_is_set (PORTA, 0);
e4: d8 9b sbis 0x1b, 0 ; 27
e6: fe cf rjmp .-4 ; 0xe4
But I get this code when testing for bit clear:
while (MY_PORTA.B0 == 1);
e8: d8 99 sbic 0x1b, 0 ; 27
ea: fe cf rjmp .-4 ; 0xe8
loop_until_bit_is_clear (PORTA, 0);
ec: 8b b3 in r24, 0x1b ; 27
ee: 99 27 eor r25, r25
f0: 9c 01 movw r18, r24
f2: 21 70 andi r18, 0x01 ; 1
f4: 30 70 andi r19, 0x00 ; 0
f6: 80 fd sbrc r24, 0
f8: f9 cf rjmp .-14 ; 0xec
Which looks to me like a place where gcc could do better optimization.
>
> P.S. Could anyone replying to this email please send me a copy
> (craig_AT_student.usyd.edu.au) as I'm having some difficulty joining the
> mailing list.
I can manually subscribe you if you wish.
Ted Roth