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[avr-gcc-list] switch/case optimisation in TWI ISR
From: |
David Bourgeois |
Subject: |
[avr-gcc-list] switch/case optimisation in TWI ISR |
Date: |
Fri, 23 Dec 2005 17:17:08 +0100 |
User-agent: |
Opera M2/8.51 (Win32, build 7712) |
I have a TWI interrupt routine inspired from the proycon avrlib and which
handles multi-master transmissions in an atmega48.
It's basically a sequence of cases for every value of the twi status.
Right now, my twi code is 780 bytes long but 292 are for the SWITCH alone,
while only 266 are for what I'm actually doing in the cases.
Is there a better way to write this? I've been told that a if/else if
sequence could be more efficient but can't really understand why. I guess
this also depends on the compiler. What about AVR-GCC in such a case?
And even if I have to write all this ISR in assembler, could I be able to
reduce this code significantly?
Thanks for your advices,
David Bourgeois
My code looks like this:
switch(TW_STATUS)
{
/* Master General */
case TW_START: // 0x08: Sent
start condition
case TW_REP_START: // 0x10: Sent
repeated start condition
i2cSendByte(I2cDeviceAddrRW); // send device
address
break;
/* Master Transmitter & Receiver status codes */
case TW_MT_SLA_ACK: // 0x18: Slave
address acknowledged
case TW_MT_DATA_ACK: // 0x28: Data
acknowledged
and the disassembler:
switch(TW_STATUS)
ade: 80 91 b9 00 lds r24, 0x00B9
ae2: 99 27 eor r25, r25
ae4: 88 7f andi r24, 0xF8 ; 248
ae6: 90 70 andi r25, 0x00 ; 0
ae8: 80 36 cpi r24, 0x60 ; 96
aea: 91 05 cpc r25, r1
aec: 09 f4 brne .+2 ; 0xaf0
aee: c7 c0 rjmp .+398 ; 0xc7e
af0: 81 36 cpi r24, 0x61 ; 97
af2: 91 05 cpc r25, r1
af4: 0c f0 brlt .+2 ; 0xaf8
af6: 3d c0 rjmp .+122 ; 0xb72
af8: 88 32 cpi r24, 0x28 ; 40
afa: 91 05 cpc r25, r1
afc: 09 f4 brne .+2 ; 0xb00
afe: 85 c0 rjmp .+266 ; 0xc0a
b00: 89 32 cpi r24, 0x29 ; 41
b02: 91 05 cpc r25, r1
- [avr-gcc-list] switch/case optimisation in TWI ISR,
David Bourgeois <=