Re: [avr-gcc-list] Difficulties switching from Mega103 to Mega128

[Brian Dean]

On Tue, Aug 12, 2003 at 08:04:43PM -0500, Scott and Roxanne Munns wrote:

> It appears that my colleague may have solved the problem between the
> Mega103 and the Mega128 in Mega103 compatibility mode today.  The
> timing and presentation of address and data info on the external
> memory interface has definitely changed (try comparing timing
> diagrams of both processors).  It seems that inserting a "nop" in
> between any consecutive reads and writes through the external memory
> interface "solves" the problem.  Since the code was written in
> assembly, it was easy to find and change the behavior.  As we learn
> more about the exact failure mode and whether this is an Atmel
> issue, LCD display driver issue, or just a bad combination of the
> two, I'll post updates to the list.

Maybe you've already been down this path, but the ATmega128 has a
programmable wait state delay.  See the "External Memory Control
Register A" (XMCRA) register (page 29 of the datasheet).  Perhaps that
will help?

Cheers,
-Brian
-- 
Brian Dean, address@hidden
BDMICRO - Maker of the MAVRIC ATmega128 Dev Board
http://www.bdmicro.com/