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Re: [avr-gcc-list] ATmega 128 Watchdog Anybody?
From: |
Peter Bosscha |
Subject: |
Re: [avr-gcc-list] ATmega 128 Watchdog Anybody? |
Date: |
Tue, 04 Jun 2002 07:30:51 +0200 |
Yeah,
Looks to me as if Atmel decided to change the watchdog a little, the
divisor register also only loads on one of those timed accesses.
I wrote my own "mega128_wdt.h" a while ago and that seems to have fixed
it:
#define wdt_enable(timeout) \
__asm__ __volatile__ ( \
"in __tmp_reg__, __SREG__" "\n\t" \
"cli" "\n\t" \
"wdr" "\n\t" \
"out %1, %0" "\n\t" \
"out %1, %0" "\n\t" \
"out __SREG__, __tmp_reg__" "\n\t" \
: /* no outputs */ \
: "r" ((uint8_t)((timeout) | BV(WDE) |
BV(WDCE))), \
"I" (WDTCR) \
: "r0" \
)
#define wdt_disable() \
__asm__ __volatile__ ( \
"in __tmp_reg__, __SREG__" "\n\t" \
"cli" "\n\t" \
"wdr" "\n\t" \
"out %1, %0" "\n\t" \
"out %1, __zero_reg__" "\n\t" \
"out __SREG__, __tmp_reg__" \
: /* no outputs */ \
: "r" (BV(WDCE) | BV(WDE)), \
"I" (WDTCR) \
: "r0" \
)
Regards
Peter Bosscha
>>> address@hidden 06/03/02 09:01PM >>>
Did anybody tried the watchdog on the ATmega 128 with
Marc's GCC patch?
wdt.h doesn't subtract __SFR_OFFSET, but that was easily fixed.
But when I do
wdt_reset();
wdt_enable(7);
the watchdog resets the CPU in less than 200 ms, but it
should happen in about 2 seconds.
Harald Kipp
egnite Software GmbH TEL +49 (0)2323-925375
Westring 303 FAX +49 (0)2323-925374
D 44629 Herne http://www.egnite.de
Germany
Ethernut Support: http://www.ethernut.de
Ethernut Development: http://ethernut.sourceforge.net
avr-gcc-list at http://avr1.org
avr-gcc-list at http://avr1.org
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