[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [avr-gcc-list] ATMega128 AVR-GCC support
|
From: |
Peter Jansen |
|
Subject: |
Re: [avr-gcc-list] ATMega128 AVR-GCC support |
|
Date: |
Tue, 04 Dec 2001 17:17:35 +1100 |
|
User-agent: |
Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:0.9.4) Gecko/20011019 Netscape6/6.2 |
1) Are there any compiler support for the ATMega128?
Not in the current releases, attached are patches for avr-libc, gcc, and
binutils if you want to re-build the tools. Some of this is in the
binutils and gcc cvs tree already.
Their are some changes in the way avr-libc defines and uses the vector
table, but I think it should be compatiable with the previous versions.
Also I did some mods to the way Data space and IO space addresses are
defined in the iom128.h file.
Regards,
--
Peter Jansen
Smart Container
Level 1, NIC Building
Eveleigh
NSW 1430
AUSTRALIA
diff -rc3P avr-libc-20011029/include/ctype.h
avr-libc-20011029-patch-0.2/include/ctype.h
*** avr-libc-20011029/include/ctype.h Sun Oct 7 02:53:36 2001
--- avr-libc-20011029-patch-0.2/include/ctype.h Wed Nov 7 17:38:50 2001
***************
*** 12,17 ****
--- 12,21 ----
#define __ATTR_CONST__ __attribute__((__const__))
#endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
extern int isalnum(int __c) __ATTR_CONST__;
extern int isalpha(int __c) __ATTR_CONST__;
extern int isascii(int __c) __ATTR_CONST__;
***************
*** 29,32 ****
--- 33,40 ----
extern int tolower(int __c) __ATTR_CONST__;
extern int toupper(int __c) __ATTR_CONST__;
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif
diff -rc3P avr-libc-20011029/include/eeprom.h
avr-libc-20011029-patch-0.2/include/eeprom.h
*** avr-libc-20011029/include/eeprom.h Sun Oct 29 04:19:50 2000
--- avr-libc-20011029-patch-0.2/include/eeprom.h Wed Nov 7 17:42:43 2001
***************
*** 26,31 ****
--- 26,35 ----
/* return 1 if EEPROM is ready for a new read/write operation, 0 if not */
#define eeprom_is_ready() bit_is_clear(EECR, EEWE)
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
/* read one byte from EEPROM address ADDR */
extern unsigned char eeprom_rb(unsigned int addr);
***************
*** 38,43 ****
--- 42,52 ----
/* read a block of SIZE bytes from EEPROM address ADDR to BUF */
extern void eeprom_read_block(void *buf, unsigned int addr, size_t n);
+
+ #ifdef __cplusplus
+ }
+ #endif
+
/* IAR C compatibility defines */
#define _EEPUT(addr, val) eeprom_wb(addr, val)
#define _EEGET(var, addr) (var) = eeprom_rb(addr)
diff -rc3P avr-libc-20011029/include/errno.h
avr-libc-20011029-patch-0.2/include/errno.h
*** avr-libc-20011029/include/errno.h Mon Jun 5 02:53:57 2000
--- avr-libc-20011029-patch-0.2/include/errno.h Wed Nov 7 17:43:35 2001
***************
*** 3,10 ****
--- 3,18 ----
#ifndef __ERRNO_H_
#define __ERRNO_H_ 1
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
extern int errno;
+ #ifdef __cplusplus
+ }
+ #endif
+
#define EDOM 33
#define ERANGE 34
diff -rc3P avr-libc-20011029/include/interrupt.h
avr-libc-20011029-patch-0.2/include/interrupt.h
*** avr-libc-20011029/include/interrupt.h Mon Feb 12 06:18:05 2001
--- avr-libc-20011029-patch-0.2/include/interrupt.h Wed Nov 7 17:40:30 2001
***************
*** 6,11 ****
--- 6,15 ----
#define sei() __asm__ __volatile__ ("sei" ::)
#define cli() __asm__ __volatile__ ("cli" ::)
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
extern inline void enable_external_int (unsigned char ints)
{
#ifdef EIMSK
***************
*** 24,27 ****
--- 28,35 ----
#endif
}
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif
diff -rc3P avr-libc-20011029/include/io-avr.h
avr-libc-20011029-patch-0.2/include/io-avr.h
*** avr-libc-20011029/include/io-avr.h Sun Oct 29 04:19:35 2000
--- avr-libc-20011029-patch-0.2/include/io-avr.h Tue Nov 6 19:06:14 2001
***************
*** 22,27 ****
--- 22,29 ----
# include <ioat94k.h>
#elif defined (__AVR_ATmega103__)
# include <iom103.h>
+ #elif defined (__AVR_ATmega128__)
+ # include <iom128.h>
#elif defined (__AVR_ATmega603__)
# include <iom603.h>
#elif defined (__AVR_ATmega32__)
diff -rc3P avr-libc-20011029/include/io.h
avr-libc-20011029-patch-0.2/include/io.h
*** avr-libc-20011029/include/io.h Sat Apr 1 23:07:05 2000
--- avr-libc-20011029-patch-0.2/include/io.h Wed Nov 7 17:37:23 2001
***************
*** 13,19 ****
--- 13,27 ----
#define outb outp
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
#include <io-avr.h>
#include <iomacros.h>
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* _IO_H_ */
diff -rc3P avr-libc-20011029/include/io1200.h
avr-libc-20011029-patch-0.2/include/io1200.h
*** avr-libc-20011029/include/io1200.h Sun Oct 29 04:18:09 2000
--- avr-libc-20011029-patch-0.2/include/io1200.h Mon Nov 19 14:49:38 2001
***************
*** 80,90 ****
#define SREG 0x3F
/* Interrupt vectors (byte addresses) */
- #define RESET_vect (0x00)
- #define INT0_vect (0x02)
- #define TIMER0_OVF_vect (0x04)
- #define ANA_COMP_vect (0x06)
#define INT_VECT_SIZE (0x08)
/* Bit numbers */
--- 80,91 ----
#define SREG 0x3F
/* Interrupt vectors (byte addresses) */
+ #define SIG_INTERRUPT0 _vector_1
+ #define SIG_OVERFLOW0 _vector_2
+ #define SIG_ADC _vector_3
+
+ #define END_VECTOR (3)
#define INT_VECT_SIZE (0x08)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/io2313.h
avr-libc-20011029-patch-0.2/include/io2313.h
*** avr-libc-20011029/include/io2313.h Tue Jun 13 03:44:20 2000
--- avr-libc-20011029-patch-0.2/include/io2313.h Mon Nov 19 14:50:10 2001
***************
*** 106,130 ****
/* Interrupt Vector Definitions */
/*==============================*/
! /* NB! vectors are specified as byte addresses */
!
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER1_CAPT_vect (0x06)
! #define TIMER1_COMPA_vect (0x08)
! #define TIMER1_OVF_vect (0x0A)
! #define TIMER0_OVF_vect (0x0C)
! #define UART_RX_vect (0x0E)
! #define UART_UDRE_vect (0x10)
! #define UART_TX_vect (0x12)
! #define ANA_COMP_vect (0x14)
#define INT_VECT_SIZE (0x16)
!
/*
! The Register Bit names are represented by their bit number (0-7).
! */
/* General Interrupt MaSK register */
#define INT1 7
--- 106,128 ----
/* Interrupt Vector Definitions */
/*==============================*/
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INPUT_CAPTURE1 _vector_3
! #define SIG_OUTPUT_COMPARE1A _vector_4
! #define SIG_OVERFLOW1 _vector_5
! #define SIG_OVERFLOW0 _vector_6
! #define SIG_UART_RECV _vector_7
! #define SIG_UART_DATA _vector_8
! #define SIG_UART_TRANS _vector_9
! #define SIG_COMPARATOR _vector_10
+ #define END_VECTOR (10)
#define INT_VECT_SIZE (0x16)
!
/*
! * The Register Bit names are represented by their bit number (0-7).
! */
/* General Interrupt MaSK register */
#define INT1 7
diff -rc3P avr-libc-20011029/include/io2323.h
avr-libc-20011029-patch-0.2/include/io2323.h
*** avr-libc-20011029/include/io2323.h Wed Jul 19 20:53:37 2000
--- avr-libc-20011029-patch-0.2/include/io2323.h Mon Nov 19 14:51:06 2001
***************
*** 67,78 ****
/* Interrupt Vector Definitions */
/*==============================*/
! /* NB! vectors are specified as byte addresses */
!
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define TIMER0_OVF_vect (0x04)
#define INT_VECT_SIZE (0x06)
/*
--- 67,76 ----
/* Interrupt Vector Definitions */
/*==============================*/
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_OVERFLOW0 _vector_2
+ #define END_VECTOR (2)
#define INT_VECT_SIZE (0x06)
/*
diff -rc3P avr-libc-20011029/include/io2333.h
avr-libc-20011029-patch-0.2/include/io2333.h
*** avr-libc-20011029/include/io2333.h Tue Jun 13 03:44:44 2000
--- avr-libc-20011029-patch-0.2/include/io2333.h Mon Nov 19 14:51:32 2001
***************
*** 140,163 ****
/* Interrupt Vector Definitions */
/* */
! /* NB! vectors are specified as byte addresses */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER1_CAPT_vect (0x06)
! #define TIMER1_COMPA_vect (0x08)
! #define TIMER1_OVF_vect (0x0A)
! #define TIMER0_OVF_vect (0x0C)
! #define SPI_STC_vect (0x0E)
! #define UART_RX_vect (0x10)
! #define UART_UDRE_vect (0x12)
! #define UART_TX_vect (0x14)
! #define ADC_vect (0x16)
! #define EE_RDY_vect (0x18)
! #define ANA_COMP_vect (0x1A)
!
! #define INT_VECT_SIZE (0x1C)
/*
The Register Bit names are represented by their bit number (0-7).
--- 140,161 ----
/* Interrupt Vector Definitions */
/* */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_OUTPUT_CAPTURE1 _vector_3
! #define SIG_OUTPUT_COMPARE1A _vector_4
! #define SIG_OVERFLOW1 _vector_5
! #define SIG_OVERFLOW0 _vector_6
! #define SIG_SPI _vector_7
! #define SIG_UART0_RECV _vector_8
! #define SIG_UART0_DATA _vector_9
! #define SIG_UART0_TRANS _vector_10
! #define SIG_ADC _vector_11
! #define SIG_EEPROM_READY _vector_12
! #define SIG_COMPARATOR _vector_13
! #define END_VECTOR (34)
! #define INT_VECT_SIZE (0x1c)
/*
The Register Bit names are represented by their bit number (0-7).
diff -rc3P avr-libc-20011029/include/io2343.h
avr-libc-20011029-patch-0.2/include/io2343.h
*** avr-libc-20011029/include/io2343.h Mon Nov 19 14:51:53 2001
--- avr-libc-20011029-patch-0.2/include/io2343.h Mon Nov 19 14:51:51 2001
***************
*** 67,78 ****
/* Interrupt Vector Definitions */
/*==============================*/
! /* NB! vectors are specified as byte addresses */
!
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define TIMER0_OVF_vect (0x04)
#define INT_VECT_SIZE (0x06)
/*
--- 67,76 ----
/* Interrupt Vector Definitions */
/*==============================*/
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_OVERFLOW0 _vector_2
+ #define END_VECTOR (2)
#define INT_VECT_SIZE (0x06)
/*
diff -rc3P avr-libc-20011029/include/io4414.h
avr-libc-20011029-patch-0.2/include/io4414.h
*** avr-libc-20011029/include/io4414.h Tue Jun 13 03:46:14 2000
--- avr-libc-20011029-patch-0.2/include/io4414.h Mon Nov 19 14:52:12 2001
***************
*** 138,160 ****
/* Interrupt Vector Definitions */
/*==============================*/
! /* NB! vectors are specified as byte addresses */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER1_CAPT_vect (0x06)
! #define TIMER1_COMPA_vect (0x08)
! #define TIMER1_COMPB_vect (0x0A)
! #define TIMER1_OVF_vect (0x0C)
! #define TIMER0_OVF_vect (0x0E)
! #define SPI_STC_vect (0x10)
! #define UART_RX_vect (0x12)
! #define UART_UDRE_vect (0x14)
! #define UART_TX_vect (0x16)
! #define ANA_COMP_vect (0x18)
!
! #define INT_VECT_SIZE (0x1A)
/*
The Register Bit names are represented by their bit number (0-7).
--- 138,158 ----
/* Interrupt Vector Definitions */
/*==============================*/
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INPUT_CAPTURE1 _vector_3
! #define SIG_OUTPUT_COMPARE1A _vector_4
! #define SIG_OUTPUT_COMPARE1B _vector_5
! #define SIG_OVERFLOW1 _vector_6
! #define SIG_OVERFLOW0 _vector_7
! #define SIG_SPI _vector_8
! #define SIG_UART_RECV _vector_9
! #define SIG_UART_DATA _vector_10
! #define SIG_UART_TRANS _vector_11
! #define SIG_ADC _vector_12
! #define END_VECTOR (12)
! #define INT_VECT_SIZE (0x1a)
/*
The Register Bit names are represented by their bit number (0-7).
diff -rc3P avr-libc-20011029/include/io4433.h
avr-libc-20011029-patch-0.2/include/io4433.h
*** avr-libc-20011029/include/io4433.h Tue Jun 13 03:46:04 2000
--- avr-libc-20011029-patch-0.2/include/io4433.h Mon Nov 19 14:52:29 2001
***************
*** 140,163 ****
/* Interrupt Vector Definitions */
/* */
! /* NB! vectors are specified as byte addresses */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER1_CAPT_vect (0x06)
! #define TIMER1_COMPA_vect (0x08)
! #define TIMER1_OVF_vect (0x0A)
! #define TIMER0_OVF_vect (0x0C)
! #define SPI_STC_vect (0x0E)
! #define UART_RX_vect (0x10)
! #define UART_UDRE_vect (0x12)
! #define UART_TX_vect (0x14)
! #define ADC_vect (0x16)
! #define EE_RDY_vect (0x18)
! #define ANA_COMP_vect (0x1A)
!
! #define INT_VECT_SIZE (0x1C)
/*
The Register Bit names are represented by their bit number (0-7).
--- 140,161 ----
/* Interrupt Vector Definitions */
/* */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INPUT_CAPTURE1 _vector_3
! #define SIG_OUTPUT_COMPARE1A _vector_4
! #define SIG_OVERFLOW1 _vector_5
! #define SIG_OVERFLOW0 _vector_6
! #define SIG_SPI _vector_7
! #define SIG_UART_RECV _vector_8
! #define SIG_UART_DATA _vector_9
! #define SIG_UART_TRANS _vector_10
! #define SIG_ADC _vector_11
! #define SIG_EEPROM_READY _vector_12
! #define SIG_COMPARATOR _vector_13
! #define END_VECTOR (13)
! #define INT_VECT_SIZE (0x1c)
/*
The Register Bit names are represented by their bit number (0-7).
diff -rc3P avr-libc-20011029/include/io4434.h
avr-libc-20011029-patch-0.2/include/io4434.h
*** avr-libc-20011029/include/io4434.h Tue Jun 13 03:46:37 2000
--- avr-libc-20011029-patch-0.2/include/io4434.h Mon Nov 19 14:52:42 2001
***************
*** 164,189 ****
/* Interrupt Vector Definitions */
/* */
! /* NB! vectors are specified as byte addresses */
!
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER2_COMP_vect (0x06)
! #define TIMER2_OVF_vect (0x08)
! #define TIMER1_CAPT_vect (0x0A)
! #define TIMER1_COMPA_vect (0x0C)
! #define TIMER1_COMPB_vect (0x0E)
! #define TIMER1_OVF_vect (0x10)
! #define TIMER0_OVF_vect (0x12)
! #define SPI_STC_vect (0x14)
! #define UART_RX_vect (0x16)
! #define UART_UDRE_vect (0x18)
! #define UART_TX_vect (0x1A)
! #define ADC_vect (0x1C)
! #define EE_RDY_vect (0x1E)
! #define ANA_COMP_vect (0x20)
#define INT_VECT_SIZE (0x22)
/*
--- 164,187 ----
/* Interrupt Vector Definitions */
/* */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_OUTPUT_COMPARE2 _vector_3
! #define SIG_OVERFLOW2 _vector_4
! #define SIG_INPUT_CAPTURE1 _vector_5
! #define SIG_OUTPUT_COMPARE1A _vector_6
! #define SIG_OUTPUT_COMPARE1B _vector_7
! #define SIG_OVERFLOW1 _vector_8
! #define SIG_OVERFLOW0 _vector_9
! #define SIG_SPI _vector_10
! #define SIG_UART_RECV _vector_11
! #define SIG_UART_DATA _vector_12
! #define SIG_UART_TRANS _vector_13
! #define SIG_ADC _vector_14
! #define SIG_EEPROM_READY _vector_15
! #define SIG_COMPARATOR _vector_16
+ #define END_VECTOR (16)
#define INT_VECT_SIZE (0x22)
/*
diff -rc3P avr-libc-20011029/include/io76c711.h
avr-libc-20011029-patch-0.2/include/io76c711.h
*** avr-libc-20011029/include/io76c711.h Thu Nov 2 05:17:00 2000
--- avr-libc-20011029-patch-0.2/include/io76c711.h Mon Nov 19 14:52:59 2001
***************
*** 106,128 ****
the entire program memory address space.
Assuming JMP for now - could be wrong, ask Atmel to be sure... */
! #define RESET_vect (0x00)
! #define SUSP_RESM_vect (0x04)
! #define INT0_vect (0x08)
! #define TIMER1_CAPT_vect (0x0C)
! #define TIMER1_COMPA_vect (0x10)
! #define TIMER1_COMPB_vect (0x14)
! #define TIMER1_OVF_vect (0x18)
! #define TIMER0_OVF_vect (0x1C)
! #define SPI_STC_vect (0x20)
! #define TDMAC_vect (0x24)
! #define UART0_vect (0x28)
! #define RDMAC_vect (0x2C)
! #define USB_HW_vect (0x30)
! #define UART1_vect (0x34)
! #define INT1_vect (0x38)
! #define INT_VECT_SIZE (0x3C)
/* Bit numbers */
--- 106,127 ----
the entire program memory address space.
Assuming JMP for now - could be wrong, ask Atmel to be sure... */
! #define SIG_SUSPEND_RESUME _vector_1
! #define SIG_INTERRUPT0 _vector_2
! #define SIG_INPUT_CAPTURE1 _vector_3
! #define SIG_OUTPUT_COMPARE1A _vector_4
! #define SIG_OUTPUT_COMPARE1B _vector_5
! #define SIG_OVERFLOW1 _vector_6
! #define SIG_OVERFLOW0 _vector_7
! #define SIG_SPI _vector_8
! #define SIG_TDMAC _vector_9
! #define SIG_UART0 _vector_10
! #define SIG_RDMAC _vector_11
! #define SIG_UART1 _vector_12
! #define SIG_INTERRUPT0 _vector_13
! #define END_VECTOR (13)
! #define INT_VECT_SIZE (0x3c)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/io8515.h
avr-libc-20011029-patch-0.2/include/io8515.h
*** avr-libc-20011029/include/io8515.h Tue Jun 13 03:46:54 2000
--- avr-libc-20011029-patch-0.2/include/io8515.h Mon Nov 19 14:53:49 2001
***************
*** 138,160 ****
/* Interrupt Vector Definitions */
/*==============================*/
! /* NB! vectors are specified as byte addresses */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER1_CAPT_vect (0x06)
! #define TIMER1_COMPA_vect (0x08)
! #define TIMER1_COMPB_vect (0x0A)
! #define TIMER1_OVF_vect (0x0C)
! #define TIMER0_OVF_vect (0x0E)
! #define SPI_STC_vect (0x10)
! #define UART_RX_vect (0x12)
! #define UART_UDRE_vect (0x14)
! #define UART_TX_vect (0x16)
! #define ANA_COMP_vect (0x18)
!
! #define INT_VECT_SIZE (0x1A)
/*
The Register Bit names are represented by their bit number (0-7).
--- 138,158 ----
/* Interrupt Vector Definitions */
/*==============================*/
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INPUT_CAPTURE1 _vector_3
! #define SIG_OUTPUT_COMPARE1A _vector_4
! #define SIG_OUTPUT_COMPARE1B _vector_5
! #define SIG_OVERFLOW1 _vector_6
! #define SIG_OVERFLOW0 _vector_7
! #define SIG_SPI _vector_8
! #define SIG_UART_RECV _vector_9
! #define SIG_UART_DATA _vector_10
! #define SIG_UART_TRANS _vector_11
! #define SIG_COMPARATOR _vector_12
! #define END_VECTOR (12)
! #define INT_VECT_SIZE (0x1a)
/*
The Register Bit names are represented by their bit number (0-7).
diff -rc3P avr-libc-20011029/include/io8534.h
avr-libc-20011029-patch-0.2/include/io8534.h
*** avr-libc-20011029/include/io8534.h Sun Oct 29 04:18:41 2000
--- avr-libc-20011029-patch-0.2/include/io8534.h Mon Nov 19 14:54:03 2001
***************
*** 104,119 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER1_OVF_vect (0x06)
! #define TIMER0_OVF_vect (0x08)
! #define ADC_vect (0x0A)
! #define EE_RDY_vect (0x0C)
! #define INT_VECT_SIZE (0x0E)
/* Bit numbers */
/* GIMSK */
--- 104,120 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_OVERFLOW1 _vector_3
! #define SIG_OVERFLOW0 _vector_4
! #define SIG_ADC _vector_5
! #define SIG_EEPROM_READY _vector_6
! #define END_VECTOR (6)
! #define INT_VECT_SIZE (0x0e)
+ /*
/* Bit numbers */
/* GIMSK */
diff -rc3P avr-libc-20011029/include/io8535.h
avr-libc-20011029-patch-0.2/include/io8535.h
*** avr-libc-20011029/include/io8535.h Mon Nov 19 14:54:16 2001
--- avr-libc-20011029-patch-0.2/include/io8535.h Mon Nov 19 14:54:14 2001
***************
*** 164,189 ****
/* Interrupt Vector Definitions */
/* */
! /* NB! vectors are specified as byte addresses */
!
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER2_COMP_vect (0x06)
! #define TIMER2_OVF_vect (0x08)
! #define TIMER1_CAPT_vect (0x0A)
! #define TIMER1_COMPA_vect (0x0C)
! #define TIMER1_COMPB_vect (0x0E)
! #define TIMER1_OVF_vect (0x10)
! #define TIMER0_OVF_vect (0x12)
! #define SPI_STC_vect (0x14)
! #define UART_RX_vect (0x16)
! #define UART_UDRE_vect (0x18)
! #define UART_TX_vect (0x1A)
! #define ADC_vect (0x1C)
! #define EE_RDY_vect (0x1E)
! #define ANA_COMP_vect (0x20)
#define INT_VECT_SIZE (0x22)
/*
--- 164,187 ----
/* Interrupt Vector Definitions */
/* */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_OUTPUT_COMPARE2 _vector_3
! #define SIG_OVERFLOW2 _vector_4
! #define SIG_INPUT_CAPTURE1 _vector_5
! #define SIG_OUTPUT_COMPARE1A _vector_6
! #define SIG_OUTPUT_COMPARE1B _vector_7
! #define SIG_OVERFLOW1 _vector_8
! #define SIG_OVERFLOW0 _vector_9
! #define SIG_SPI _vector_10
! #define SIG_UART_RECV _vector_11
! #define SIG_UART_DATA _vector_12
! #define SIG_UART_TRANS _vector_13
! #define SIG_ADC _vector_14
! #define SIG_EEPROM_READY _vector_15
! #define SIG_COMPARATOR _vector_16
+ #define END_VECTOR (16)
#define INT_VECT_SIZE (0x22)
/*
diff -rc3P avr-libc-20011029/include/ioat94k.h
avr-libc-20011029-patch-0.2/include/ioat94k.h
*** avr-libc-20011029/include/ioat94k.h Sun Oct 29 04:19:13 2000
--- avr-libc-20011029-patch-0.2/include/ioat94k.h Mon Nov 19 14:54:27 2001
***************
*** 193,235 ****
/* Interrupt vectors (byte addresses) */
- #define RESET_vect (0x00)
- #define FPGA_INT0_vect (0x04)
- #define INT0_vect (0x08)
- #define FPGA_INT1_vect (0x0C)
- #define INT1_vect (0x10)
- #define FPGA_INT2_vect (0x14)
- #define INT2_vect (0x18)
- #define FPGA_INT3_vect (0x1C)
- #define INT3_vect (0x20)
- #define TIMER2_COMP_vect (0x24)
- #define TIMER2_OVF_vect (0x28)
- #define TIMER1_CAPT_vect (0x2C)
- #define TIMER1_COMPA_vect (0x30)
- #define TIMER1_COMPB_vect (0x34)
- #define TIMER1_OVF_vect (0x38)
- #define TIMER0_COMP_vect (0x3C)
- #define TIMER0_OVF_vect (0x40)
- #define FPGA_INT4_vect (0x44)
- #define FPGA_INT5_vect (0x48)
- #define FPGA_INT6_vect (0x4C)
- #define FPGA_INT7_vect (0x50)
- #define UART_RX_vect (0x54)
- #define UART_UDRE_vect (0x58)
- #define UART_TX_vect (0x5C)
- #define FPGA_INT8_vect (0x60)
- #define FPGA_INT9_vect (0x64)
- #define FPGA_INT10_vect (0x68)
- #define FPGA_INT11_vect (0x6C)
- #define UART1_RX_vect (0x70)
- #define UART1_UDRE_vect (0x74)
- #define UART1_TX_vect (0x78)
- #define FPGA_INT12_vect (0x7C)
- #define FPGA_INT13_vect (0x80)
- #define FPGA_INT14_vect (0x84)
- #define FPGA_INT15_vect (0x88)
- #define TWI_INT_vect (0x8C)
#define INT_VECT_SIZE (0x90)
/* Bit numbers - XXX not here yet */
--- 193,236 ----
/* Interrupt vectors (byte addresses) */
+ #define SIG_INTERRUPT0 _vector_1
+ #define SIG_FPGA_INTERRUPT0 _vector_2
+ #define SIG_INTERRUPT1 _vector_3
+ #define SIG_FPGA_INTERRUPT1 _vector_4
+ #define SIG_INTERRUPT2 _vector_5
+ #define SIG_FPGA_INTERRUPT2 _vector_6
+ #define SIG_INTERRUPT3 _vector_7
+ #define SIG_FPGA_INTERRUPT3 _vector_8
+ #define SIG_OUTPUT_COMPARE2 _vector_9
+ #define SIG_OVERFLOW2 _vector_10
+ #define SIG_INPUT_CAPTURE1 _vector_11
+ #define SIG_OUTPUT_COMPARE1A _vector_12
+ #define SIG_OUTPUT_COMPARE1B _vector_13
+ #define SIG_OVERFLOW1 _vector_14
+ #define SIG_OUTPUT_COMPARE0 _vector_15
+ #define SIG_OVERFLOW0 _vector_16
+ #define SIG_FPGA_INTERRUPT4 _vector_17
+ #define SIG_FPGA_INTERRUPT5 _vector_18
+ #define SIG_FPGA_INTERRUPT6 _vector_19
+ #define SIG_FPGA_INTERRUPT7 _vector_20
+ #define SIG_UART0_RECV _vector_21
+ #define SIG_UART0_DATA _vector_22
+ #define SIG_UART0_TRANS _vector_23
+ #define SIG_FPGA_INTERRUPT8 _vector_24
+ #define SIG_FPGA_INTERRUPT9 _vector_25
+ #define SIG_FPGA_INTERRUPT10 _vector_26
+ #define SIG_FPGA_INTERRUPT11 _vector_27
+ #define SIG_UART1_RECV _vector_28
+ #define SIG_UART1_DATA _vector_29
+ #define SIG_UART1_TRANS _vector_30
+ #define SIG_FPGA_INTERRUPT11 _vector_31
+ #define SIG_FPGA_INTERRUPT12 _vector_32
+ #define SIG_FPGA_INTERRUPT13 _vector_33
+ #define SIG_FPGA_INTERRUPT14 _vector_34
+ #define SIG_2WIRE_SERIAL _vector_35
+
+ #define END_VECTOR (35)
#define INT_VECT_SIZE (0x90)
/* Bit numbers - XXX not here yet */
diff -rc3P avr-libc-20011029/include/iom103.h
avr-libc-20011029-patch-0.2/include/iom103.h
*** avr-libc-20011029/include/iom103.h Tue Jun 13 03:48:31 2000
--- avr-libc-20011029-patch-0.2/include/iom103.h Mon Nov 19 14:54:41 2001
***************
*** 185,215 ****
/* NB! vectors are specified as byte addresses */
! #define RESET_vect (0x00)
! #define INT0_vect (0x04)
! #define INT1_vect (0x08)
! #define INT2_vect (0x0C)
! #define INT3_vect (0x10)
! #define INT4_vect (0x14)
! #define INT5_vect (0x18)
! #define INT6_vect (0x1C)
! #define INT7_vect (0x20)
! #define TIMER2_COMP_vect (0x24)
! #define TIMER2_OVF_vect (0x28)
! #define TIMER1_CAPT_vect (0x2C)
! #define TIMER1_COMPA_vect (0x30)
! #define TIMER1_COMPB_vect (0x34)
! #define TIMER1_OVF_vect (0x38)
! #define TIMER0_COMP_vect (0x3C)
! #define TIMER0_OVF_vect (0x40)
! #define SPI_STC_vect (0x44)
! #define UART_RX_vect (0x48)
! #define UART_UDRE_vect (0x4C)
! #define UART_TX_vect (0x50)
! #define ADC_vect (0x54)
! #define EE_RDY_vect (0x58)
! #define ANA_COMP_vect (0x5C)
#define INT_VECT_SIZE (0x60)
/*
--- 185,215 ----
/* NB! vectors are specified as byte addresses */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INTERRUPT2 _vector_3
! #define SIG_INTERRUPT3 _vector_4
! #define SIG_INTERRUPT4 _vector_5
! #define SIG_INTERRUPT5 _vector_6
! #define SIG_INTERRUPT6 _vector_7
! #define SIG_INTERRUPT7 _vector_8
! #define SIG_OUTPUT_COMPARE2 _vector_9
! #define SIG_OVERFLOW2 _vector_10
! #define SIG_INPUT_CAPTURE1 _vector_11
! #define SIG_OUTPUT_COMPARE1A _vector_12
! #define SIG_OUTPUT_COMPARE1B _vector_13
! #define SIG_OVERFLOW1 _vector_14
! #define SIG_OUTPUT_COMPARE0 _vector_15
! #define SIG_OVERFLOW0 _vector_16
! #define SIG_SPI _vector_17
! #define SIG_UART_RECV _vector_18
! #define SIG_UART_DATA _vector_19
! #define SIG_UART_TRANS _vector_20
! #define SIG_ADC _vector_21
! #define SIG_EEPROM_READY _vector_22
! #define SIG_COMPARATOR _vector_23
+ #define END_VECTOR (23)
#define INT_VECT_SIZE (0x60)
/*
diff -rc3P avr-libc-20011029/include/iom128.h
avr-libc-20011029-patch-0.2/include/iom128.h
*** avr-libc-20011029/include/iom128.h Thu Jan 1 10:00:00 1970
--- avr-libc-20011029-patch-0.2/include/iom128.h Tue Nov 27 13:10:48 2001
***************
*** 0 ****
--- 1,754 ----
+ /*
+ iom128.h - AVR ATmega128 defines
+
+ Contributors:
+ Created by Peter Jansen <address@hidden>
+
+ THIS SOFTWARE IS NOT COPYRIGHTED
+
+ This source code is offered for use in the public domain. You may
+ use, modify or distribute it freely.
+
+ This code is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY
+ DISCLAIMED. This includes but is not limited to warranties of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ */
+
+ #ifndef __IOM128
+ #define __IOM128 1
+
+ #define AVR_MEGA 1
+ #define AVR_ENHANCED 1
+
+ /*
+ * Predefined SFR Addresses.
+ * NOTE: These addresses will be either DATA MEMORY or I/O MEMORY addresses,
+ * depending on how you define __SFR_OFFSET (0x0 for I/O, 0x20 for DATA).
+ * For accesses to memory locations 0x20 through to 0x5F, gcc subtracts
+ * 0x20 from the address supplied and uses an I/O instruction, rather than
+ * a data memory access instruction (I/O instructions can only address the
+ * first 64 I/O memory locations).
+ * By using the __SFR_OFFSET symbol defined as 0x20 in the header file, all
+ * special file registers (data memory addresses 0x00--0x1F), all I/O
+ * registers (data memory address 0x20--0x5F, I/O memory address 0x00--0x3F)
+ * and all extended I/O registers (data memory address 0x60--0xFF) can be
+ * used as is, without being wrapped in macros to adjust the address.
+ */
+ /* #define __SFR_OFFSET 0x0 */
+ #define __SFR_OFFSET 0x20
+
+ /* Input Pins, Port F */
+ #define PINF (0x0 + __SFR_OFFSET)
+
+ /* Input Pins, Port E */
+ #define PINE (0x1 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port E */
+ #define DDRE (0x2 + __SFR_OFFSET)
+
+ /* Data Register, Port E */
+ #define PORTE (0x3 + __SFR_OFFSET)
+
+ /* ADC Low Byte */
+ #define ADCL (0x4 + __SFR_OFFSET)
+
+ /* ADC High Byte */
+ #define ADCH (0x5 + __SFR_OFFSET)
+
+ /* ADC Control and status register */
+ #define ADCSR (0x6 + __SFR_OFFSET)
+
+ /* ADC Multiplexer select */
+ #define ADMUX (0x7 + __SFR_OFFSET)
+
+ /* Analog Comparator Control and Status Register */
+ #define ACSR (0x8 + __SFR_OFFSET)
+
+ /* USART0 Baud Rate Register Low */
+ #define UBRR0L (0x9 + __SFR_OFFSET)
+
+ /* USART0 Control and Status Register B */
+ #define UCSR0B (0xA + __SFR_OFFSET)
+
+ /* USART0 Control and Status Register A */
+ #define UCSR0A (0xB + __SFR_OFFSET)
+
+ /* USART I/O Data Register */
+ #define UDR0 (0xC + __SFR_OFFSET)
+
+ /* SPI Control Register */
+ #define SPCR (0xD + __SFR_OFFSET)
+
+ /* SPI Status Register */
+ #define SPSR (0xE + __SFR_OFFSET)
+
+ /* SPI I/O Data Register */
+ #define SPDR (0xF + __SFR_OFFSET)
+
+ /* Input Pins, Port D */
+ #define PIND (0x10 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port D */
+ #define DDRD (0x11 + __SFR_OFFSET)
+
+ /* Data Register, Port D */
+ #define PORTD (0x12 + __SFR_OFFSET)
+
+ /* Input Pins, Port C */
+ #define PINC (0x13 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port C */
+ #define DDRC (0x14 + __SFR_OFFSET)
+
+ /* Data Register, Port C */
+ #define PORTC (0x15 + __SFR_OFFSET)
+
+ /* Input Pins, Port B */
+ #define PINB (0x16 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port B */
+ #define DDRB (0x17 + __SFR_OFFSET)
+
+ /* Data Register, Port B */
+ #define PORTB (0x18 + __SFR_OFFSET)
+
+ /* Input Pins, Port A */
+ #define PINA (0x19 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port A */
+ #define DDRA (0x1A + __SFR_OFFSET)
+
+ /* Data Register, Port A */
+ #define PORTA (0x1B + __SFR_OFFSET)
+
+ /* EEPROM Control Register */
+ #define EECR (0x1C + __SFR_OFFSET)
+
+ /* EEPROM Data Register */
+ #define EEDR (0x1D + __SFR_OFFSET)
+
+ /* EEPROM Address Register Low */
+ #define EEARL (0x1E + __SFR_OFFSET)
+
+ /* EEPROM Address Register High */
+ #define EEARH (0x1F + __SFR_OFFSET)
+
+ /* Special Function I/O Register */
+ #define SFIOR (0x20 + __SFR_OFFSET)
+
+ /* Watchdog Timer Control Register */
+ #define WDTCR (0x21 + __SFR_OFFSET)
+
+ /* On-chip Debug Register */
+ #define OCDR (0x22 + __SFR_OFFSET)
+
+ /* Timer2 Output Compare Register */
+ #define OCR2 (0x23 + __SFR_OFFSET)
+
+ /* Timer/Counter 2 */
+ #define TCNT2 (0x24 + __SFR_OFFSET)
+
+ /* Timer/Counter 2 Control register */
+ #define TCCR2 (0x25 + __SFR_OFFSET)
+
+ /* T/C 1 Input Capture Register Low */
+ #define ICR1L (0x26 + __SFR_OFFSET)
+
+ /* T/C 1 Input Capture Register High */
+ #define ICR1H (0x27 + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register B Low */
+ #define OCR1BL (0x28 + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register B High */
+ #define OCR1BH (0x29 + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register A Low */
+ #define OCR1AL (0x2A + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register A High */
+ #define OCR1AH (0x2B + __SFR_OFFSET)
+
+ /* Timer/Counter 1 Low */
+ #define TCNT1L (0x2C + __SFR_OFFSET)
+
+ /* Timer/Counter 1 High */
+ #define TCNT1H (0x2D + __SFR_OFFSET)
+
+ /* Timer/Counter 1 Control and Status Register */
+ #define TCCR1B (0x2E + __SFR_OFFSET)
+
+ /* Timer/Counter 1 Control Register */
+ #define TCCR1A (0x2F + __SFR_OFFSET)
+
+ /* Timer/Counter 0 Asynchronous Control & Status Register */
+ #define ASSR (0x30 + __SFR_OFFSET)
+
+ /* Output Compare Register 0 */
+ #define OCR0 (0x31 + __SFR_OFFSET)
+
+ /* Timer/Counter 0 */
+ #define TCNT0 (0x32 + __SFR_OFFSET)
+
+ /* Timer/Counter 0 Control Register */
+ #define TCCR0 (0x33 + __SFR_OFFSET)
+
+ /* MCU Status Register */
+ #define MCUSR (0x34 + __SFR_OFFSET)
+
+ /* MCU general Control Register */
+ #define MCUCR (0x35 + __SFR_OFFSET)
+
+ /* Timer/Counter Interrupt Flag Register */
+ #define TIFR (0x36 + __SFR_OFFSET)
+
+ /* Timer/Counter Interrupt MaSK register */
+ #define TIMSK (0x37 + __SFR_OFFSET)
+
+ /* External Interrupt Flag Register */
+ #define EIFR (0x38 + __SFR_OFFSET)
+
+ /* External Interrupt MaSK register */
+ #define EIMSK (0x39 + __SFR_OFFSET)
+
+ /* External Interrupt Control Register B */
+ #define EICRB (0x3A + __SFR_OFFSET)
+
+ /* RAM Page Z select register */
+ #define RAMPZ (0x3B + __SFR_OFFSET)
+
+ /* XDIV Divide control register */
+ #define XDIV (0x3C + __SFR_OFFSET)
+
+ /* Stack Pointer Low */
+ #define SPL (0x3D + __SFR_OFFSET)
+
+ /* Stack Pointer High */
+ #define SPH (0x3E + __SFR_OFFSET)
+
+ /* Status REGister */
+ #define SREG (0x3F + __SFR_OFFSET)
+
+ /* Data Direction Register, Port F */
+ #define DDRF (0x61)
+
+ /* Data Register, Port F */
+ #define PORTF (0x62)
+
+ /* Input Pins, Port G */
+ #define PING (0x63)
+
+ /* Data Direction Register, Port G */
+ #define DDRG (0x64)
+
+ /* Data Register, Port G */
+ #define PORTG (0x65)
+
+ /* Store Program Memory Control Register */
+ #define SPMCR (0x68)
+
+ /* External Interrupt Control Register A */
+ #define EICRA (0x6A)
+
+ /* External Memory Control Register B */
+ #define XMCRB (0x6C)
+
+ /* External Memory Control Register A */
+ #define XMCRA (0x6D)
+
+ /* Oscillator Calibration Register */
+ #define OSCCAL (0x6F)
+
+ /* 2-wire Serial Interface Bit Rate Register */
+ #define TWBR (0x70)
+
+ /* 2-wire Serial Interface Status Register */
+ #define TWSR (0x71)
+
+ /* 2-wire Serial Interface Address Register */
+ #define TWAR (0x72)
+
+ /* 2-wire Serial Interface Data Register */
+ #define TWDR (0x73)
+
+ /* 2-wire Serial Interface Control Register */
+ #define TWCR (0x74)
+
+ /* Time Counter 1 Output Compare Register C Low */
+ #define OCR1CL (0x78)
+
+ /* Time Counter 1 Output Compare Register C High */
+ #define OCR1CH (0x79)
+
+ /* Timer/Counter 1 Control Register C */
+ #define TCCR1C (0x7A)
+
+ /* Extended Timer Interrupt Flag Register */
+ #define ETIFR (0x7C)
+
+ /* Extended Timer Interrupt Mask Register */
+ #define ETIMSK (0x7D)
+
+ /* Timer/Counter 3 Input Capture Register Low */
+ #define ICR3L (0x80)
+
+ /* Timer/Counter 3 Input Capture Register High */
+ #define ICR3H (0x81)
+
+ /* Timer/Counter 3 Output Compare Register C Low */
+ #define OCR3CL (0x82)
+
+ /* Timer/Counter 3 Output Compare Register C High */
+ #define OCR3CH (0x83)
+
+ /* Timer/Counter 3 Output Compare Register B Low */
+ #define OCR3BL (0x84)
+
+ /* Timer/Counter 3 Output Compare Register B High */
+ #define OCR3BH (0x85)
+
+ /* Timer/Counter 3 Output Compare Register A Low */
+ #define OCR3AL (0x86)
+
+ /* Timer/Counter 3 Output Compare Register A High */
+ #define OCR3AH (0x87)
+
+ /* Timer/Counter 3 Counter Register High */
+ #define TCNT3L (0x88)
+
+ /* Timer/Counter 3 Counter Register High */
+ #define TCNT3H (0x89)
+
+ /* Timer/Counter 3 Control Register B */
+ #define TCCR3B (0x8A)
+
+ /* Timer/Counter 3 Control Register A */
+ #define TCCR3A (0x8B)
+
+ /* Timer/Counter 3 Control Register C */
+ #define TCCR3C (0x8C)
+
+ /* USART0 Baud Rate Register High */
+ #define UBRR0H (0x90)
+
+ /* USART0 Control and Status Register C */
+ #define UCSR0C (0x95)
+
+ /* USART1 Baud Rate Register High */
+ #define UBRR1H (0x98)
+
+ /* USART1 Baud Rate Register Low*/
+ #define UBRR1L (0x99)
+
+ /* USART1 Control and Status Register B */
+ #define UCSR1B (0x9A)
+
+ /* USART1 Control and Status Register A */
+ #define UCSR1A (0x9B)
+
+ /* USART1 I/O Data Register */
+ #define UDR1 (0x9C)
+
+ /* USART1 Control and Status Register C */
+ #define UCSR1C (0x9D)
+
+ /*
+ * Interrupt Vector Definitions
+ */
+
+ #define SIG_INTERRUPT0 _vector_1
+ #define SIG_INTERRUPT1 _vector_2
+ #define SIG_INTERRUPT2 _vector_3
+ #define SIG_INTERRUPT3 _vector_4
+ #define SIG_INTERRUPT4 _vector_5
+ #define SIG_INTERRUPT5 _vector_6
+ #define SIG_INTERRUPT6 _vector_7
+ #define SIG_INTERRUPT7 _vector_8
+ #define SIG_OUTPUT_COMPARE2 _vector_9
+ #define SIG_OVERFLOW2 _vector_10
+ #define SIG_INPUT_CAPTURE1 _vector_11
+ #define SIG_OUTPUT_COMPARE1A _vector_12
+ #define SIG_OUTPUT_COMPARE1B _vector_13
+ #define SIG_OVERFLOW1 _vector_14
+ #define SIG_OUTPUT_COMPARE0 _vector_15
+ #define SIG_OVERFLOW0 _vector_16
+ #define SIG_SPI _vector_17
+ #define SIG_UART0_RECV _vector_18
+ #define SIG_UART0_DATA _vector_19
+ #define SIG_UART0_TRANS _vector_20
+ #define SIG_ADC _vector_21
+ #define SIG_EEPROM_READY _vector_22
+ #define SIG_COMPARATOR _vector_23
+ #define SIG_OUTPUT_COMPARE1C _vector_24
+ #define SIG_INPUT_CAPTURE3 _vector_25
+ #define SIG_OUTPUT_COMPARE3A _vector_26
+ #define SIG_OUTPUT_COMPARE3B _vector_27
+ #define SIG_OUTPUT_COMPARE3C _vector_28
+ #define SIG_OVERFLOW3 _vector_29
+ #define SIG_UART1_RECV _vector_30
+ #define SIG_UART1_DATA _vector_31
+ #define SIG_UART1_TRANS _vector_32
+ #define SIG_2WIRE_SERIAL _vector_33
+ #define SIG_SPM_READY _vector_34
+
+ #define END_VECTOR (34)
+ #define INT_VECT_SIZE (0x8a)
+
+ /*
+ The Register Bit names are represented by their bit number (0-7).
+ */
+
+ /* 2-wire Control Register */
+ #define TWINT 7
+ #define TWEA 6
+ #define TWSTA 5
+ #define TWSTO 4
+ #define TWWC 3
+ #define TWEN 2
+ #define TWIE 0
+
+ /* 2-wire Address Register */
+ #define TWA6 7
+ #define TWA5 6
+ #define TWA4 5
+ #define TWA3 4
+ #define TWA2 3
+ #define TWA1 2
+ #define TWA0 1
+ #define TWGCE 0
+
+ /* 2-wire Status Register */
+ #define TWS7 7
+ #define TWS6 6
+ #define TWS5 5
+ #define TWS4 4
+ #define TWS3 3
+ #define TWPS1 1
+ #define TWPS0 0
+
+ /* External Memory Control Register A */
+ #define SRL2 6
+ #define SRL1 5
+ #define SRL0 4
+ #define SRW01 3
+ #define SRW00 2
+ #define SRW11 1
+
+ /* External Memory Control Register B */
+ #define XMBK 7
+ #define XMM2 2
+ #define XMM1 1
+ #define XMM0 0
+
+ /* XDIV Divide control register*/
+ #define XDIVEN 7
+ #define XDIV6 6
+ #define XDIV5 5
+ #define XDIV4 4
+ #define XDIV3 3
+ #define XDIV2 2
+ #define XDIV1 1
+ #define XDIV0 0
+
+ /* RAM Page Z select register */
+ #define RAMPZ0 0
+
+ /* External Interrupt Control Register A */
+ #define ISC31 7
+ #define ISC30 6
+ #define ISC21 5
+ #define ISC20 4
+ #define ISC11 3
+ #define ISC10 2
+ #define ISC01 1
+ #define ISC00 0
+
+ /* External Interrupt Control Register B */
+ #define ISC71 7
+ #define ISC70 6
+ #define ISC61 5
+ #define ISC60 4
+ #define ISC51 3
+ #define ISC50 2
+ #define ISC41 1
+ #define ISC40 0
+
+ /* Store Program Memory Control Register */
+ #define SPMIE 7
+ #define RWWSB 6
+ #define RWWSRE 4
+ #define BLBSET 3
+ #define PGWRT 2
+ #define PGERS 1
+ #define SPMEN 0
+
+ /* External Interrupt MaSK register */
+ #define INT7 7
+ #define INT6 6
+ #define INT5 5
+ #define INT4 4
+ #define INT3 3
+ #define INT2 2
+ #define INT1 1
+ #define INT0 0
+
+ /* External Interrupt Flag Register */
+ #define INTF7 7
+ #define INTF6 6
+ #define INTF5 5
+ #define INTF4 4
+
+ /* Timer/Counter Interrupt MaSK register */
+ #define OCIE2 7
+ #define TOIE2 6
+ #define TICIE1 5
+ #define OCIE1A 4
+ #define OCIE1B 3
+ #define TOIE1 2
+ #define OCIE0 1
+ #define TOIE0 0
+
+ /* Timer/Counter Interrupt Flag Register */
+ #define OCF2 7
+ #define TOV2 6
+ #define ICF1 5
+ #define OCF1A 4
+ #define OCF1B 3
+ #define TOV1 2
+ #define OCF0 1
+ #define TOV0 0
+
+ /* Extended Timer Interrupt MaSK register */
+ #define TICIE3 5
+ #define OCIE3A 4
+ #define OCIE3B 3
+ #define TOIE3 2
+ #define OCIE3C 1
+ #define OCIE1C 0
+
+ /* Extended Timer Interrupt Flag Register */
+ #define ICF3 5
+ #define OCF3A 4
+ #define OCF3B 3
+ #define TOV3 2
+ #define OCF3C 1
+ #define OCF1C 0
+
+ /* MCU general Control Register */
+ #define SRE 7
+ #define SRW 6
+ #define SE 5
+ #define SM1 4
+ #define SM0 3
+ #define SM2 2
+ #define IVSEL 1
+ #define IVCE 0
+
+ /* MCU Status Register */
+ #define JTD 7
+ #define JTRF 4
+ #define WDRF 3
+ #define BORF 2
+ #define EXTRF 1
+ #define PORF 0
+
+ /* Timer/Counter Control Register */
+ #define FOC 7
+ #define WGM0 6
+ #define COM1 5
+ #define COM0 4
+ #define WGM1 3
+ #define CS2 2
+ #define CS1 1
+ #define CS0 0
+
+ /* Timer/Counter 0 Asynchronous Control & Status Register */
+ #define AS0 3
+ #define TCN0UB 2
+ #define OCR0UB 1
+ #define TCR0UB 0
+
+ /* Timer/Counter Control Register A */
+ #define COMA1 7
+ #define COMA0 6
+ #define COMB1 5
+ #define COMB0 4
+ #define COMC1 3
+ #define COMC0 2
+ #define WGMA1 1
+ #define WGMA0 0
+
+ /* Timer/Counter Control and Status Register B */
+ #define ICNC 7
+ #define ICES 6
+ #define WGMB3 4
+ #define WGMB2 3
+ #define CSB2 2
+ #define CSB1 1
+ #define CSB0 0
+
+ /* Timer/Counter Control Register C */
+ #define FOCA 7
+ #define FOCB 6
+ #define FOCC 5
+
+ /* On-chip Debug Register */
+ #define OCDR7 7
+ #define OCDR6 6
+ #define OCDR5 5
+ #define OCDR4 4
+ #define OCDR3 3
+ #define OCDR2 2
+ #define OCDR1 1
+ #define OCDR0 0
+
+ /* Watchdog Timer Control Register */
+ #define WDCE 4
+ #define WDE 3
+ #define WDP2 2
+ #define WDP1 1
+ #define WDP0 0
+
+ /* Special Function I/O Register */
+ #define TSM 7
+ #define ADHSM 4
+ #define ACME 3
+ #define PUD 2
+ #define PSR0 1
+ #define PSR321 0
+
+ /* EEPROM Control Register */
+ #define EERIE 3
+ #define EEMWE 2
+ #define EEWE 1
+ #define EERE 0
+
+ /* Port Data Register */
+ #define PORT7 7
+ #define PORT6 6
+ #define PORT5 5
+ #define PORT4 4
+ #define PORT3 3
+ #define PORT2 2
+ #define PORT1 1
+ #define PORT0 0
+
+ /* Port Data Direction Register */
+ #define DD7 7
+ #define DD6 6
+ #define DD5 5
+ #define DD4 4
+ #define DD3 3
+ #define DD2 2
+ #define DD1 1
+ #define DD0 0
+
+ /* Port Input Pins */
+ #define PIN7 7
+ #define PIN6 6
+ #define PIN5 5
+ #define PIN4 4
+ #define PIN3 3
+ #define PIN2 2
+ #define PIN1 1
+ #define PIN0 0
+
+ /* Status Register */
+ #define SREG_I 7
+ #define SREG_T 6
+ #define SREG_H 5
+ #define SREG_S 4
+ #define SREG_V 3
+ #define SREG_N 2
+ #define SREG_Z 1
+ #define SREG_C 0
+
+ /* SPI Status Register */
+ #define SPIF 7
+ #define WCOL 6
+ #define SPI2X 0
+
+ /* SPI Control Register */
+ #define SPIE 7
+ #define SPE 6
+ #define DORD 5
+ #define MSTR 4
+ #define CPOL 3
+ #define CPHA 2
+ #define SPR1 1
+ #define SPR0 0
+
+ /* USART Register C */
+ #define UMSEL 6
+ #define UPM1 5
+ #define UPM0 4
+ #define USBS 3
+ #define UCSZ1 2
+ #define UCSZ0 1
+ #define UCPOL 0
+
+ /* USART Status Register A */
+ #define RXC 7
+ #define TXC 6
+ #define UDRE 5
+ #define FE 4
+ #define OVR 3 /* This definition differs from the databook */
+ /*definition to avoid problems with the OR instruction */
+
+ /* USART Control Register */
+ #define RXCIE 7
+ #define TXCIE 6
+ #define UDRIE 5
+ #define RXEN 4
+ #define TXEN 3
+ #define UCSZ 2
+ #define RXB8 1
+ #define TXB8 0
+
+ /* Analog Comparator Control and Status Register */
+ #define ACD 7
+ #define ACBG 6
+ #define ACO 5
+ #define ACI 4
+ #define ACIE 3
+ #define ACIC 2
+ #define ACIS1 1
+ #define ACIS0 0
+
+ /* ADC Control and status register */
+ #define ADEN 7
+ #define ADSC 6
+ #define ADFR 5
+ #define ADIF 4
+ #define ADIE 3
+ #define ADPS2 2
+ #define ADPS1 1
+ #define ADPS0 0
+
+ /* ADC Multiplexer select */
+ #define REFS1 7
+ #define REFS0 6
+ #define ADLAR 5
+ #define MUX4 4
+ #define MUX3 3
+ #define MUX2 2
+ #define MUX1 1
+ #define MUX0 0
+
+ /* Pointer definition */
+ #define XL r26
+ #define XH r27
+ #define YL r28
+ #define YH r29
+ #define ZL r30
+ #define ZH r31
+
+ /* Constants */
+ #define RAMEND 0x10FF /* Last On-Chip SRAM Location */
+ #define XRAMEND 0xFFFF
+ #define E2END 0x0FFF
+ #define FLASHEND 0x1FFFF
+
+ #endif /* __IOM128 */
diff -rc3P avr-libc-20011029/include/iom128.h~
avr-libc-20011029-patch-0.2/include/iom128.h~
*** avr-libc-20011029/include/iom128.h~ Thu Jan 1 10:00:00 1970
--- avr-libc-20011029-patch-0.2/include/iom128.h~ Tue Nov 20 12:39:15 2001
***************
*** 0 ****
--- 1,751 ----
+ /*
+ iom128.h - AVR ATmega128 defines
+
+ Contributors:
+ Created by Peter Jansen <address@hidden>
+
+ THIS SOFTWARE IS NOT COPYRIGHTED
+
+ This source code is offered for use in the public domain. You may
+ use, modify or distribute it freely.
+
+ This code is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY
+ DISCLAIMED. This includes but is not limited to warranties of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ */
+
+ #ifndef __IOM128
+ #define __IOM128 1
+
+ #define AVR_MEGA 1
+ #define AVR_ENHANCED 1
+
+ /*
+ * Predefined SFR Addresses.
+ * NOTE: These addresses will be either DATA MEMORY or I/O MEMORY addresses,
+ * depending on how you define __SFR_OFFSET (0x0 for I/O, 0x20 for DATA).
+ * For accesses to memory locations 0x20 through to 0x5F, gcc subtracts
+ * 0x20 from the address supplied and uses an I/O instruction, rather than
+ * a data memory access instruction (I/O instructions can only address the
+ * first 64 I/O memory locations).
+ * By using the __SFR_OFFSET symbol defined as 0x20 in the header file, all
+ * special file registers (data memory addresses 0x00--0x1F), all I/O
+ * registers (data memory address 0x20--0x5F, I/O memory address 0x00--0x3F)
+ * and all extended I/O registers (data memory address 0x60--0xFF) can be
+ * used as is, without being wrapped in macros to adjust the address.
+ */
+ /* #define __SFR_OFFSET 0x0 */
+ #define __SFR_OFFSET 0x20
+
+ /* Input Pins, Port F */
+ #define PINF (0x0 + __SFR_OFFSET)
+
+ /* Input Pins, Port E */
+ #define PINE (0x1 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port E */
+ #define DDRE (0x2 + __SFR_OFFSET)
+
+ /* Data Register, Port E */
+ #define PORTE (0x3 + __SFR_OFFSET)
+
+ /* ADC Low Byte */
+ #define ADCL (0x4 + __SFR_OFFSET)
+
+ /* ADC High Byte */
+ #define ADCH (0x5 + __SFR_OFFSET)
+
+ /* ADC Control and status register */
+ #define ADCSR (0x6 + __SFR_OFFSET)
+
+ /* ADC Multiplexer select */
+ #define ADMUX (0x7 + __SFR_OFFSET)
+
+ /* Analog Comparator Control and Status Register */
+ #define ACSR (0x8 + __SFR_OFFSET)
+
+ /* USART0 Baud Rate Register Low */
+ #define UBRR0L (0x9 + __SFR_OFFSET)
+
+ /* USART0 Control and Status Register B */
+ #define UCSR0B (0xA + __SFR_OFFSET)
+
+ /* USART0 Control and Status Register A */
+ #define UCSR0A (0xB + __SFR_OFFSET)
+
+ /* USART I/O Data Register */
+ #define UDR0 (0xC + __SFR_OFFSET)
+
+ /* SPI Control Register */
+ #define SPCR (0xD + __SFR_OFFSET)
+
+ /* SPI Status Register */
+ #define SPSR (0xE + __SFR_OFFSET)
+
+ /* SPI I/O Data Register */
+ #define SPDR (0xF + __SFR_OFFSET)
+
+ /* Input Pins, Port D */
+ #define PIND (0x10 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port D */
+ #define DDRD (0x11 + __SFR_OFFSET)
+
+ /* Data Register, Port D */
+ #define PORTD (0x12 + __SFR_OFFSET)
+
+ /* Input Pins, Port C */
+ #define PINC (0x13 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port C */
+ #define DDRC (0x14 + __SFR_OFFSET)
+
+ /* Data Register, Port C */
+ #define PORTC (0x15 + __SFR_OFFSET)
+
+ /* Input Pins, Port B */
+ #define PINB (0x16 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port B */
+ #define DDRB (0x17 + __SFR_OFFSET)
+
+ /* Data Register, Port B */
+ #define PORTB (0x18 + __SFR_OFFSET)
+
+ /* Input Pins, Port A */
+ #define PINA (0x19 + __SFR_OFFSET)
+
+ /* Data Direction Register, Port A */
+ #define DDRA (0x1A + __SFR_OFFSET)
+
+ /* Data Register, Port A */
+ #define PORTA (0x1B + __SFR_OFFSET)
+
+ /* EEPROM Control Register */
+ #define EECR (0x1C + __SFR_OFFSET)
+
+ /* EEPROM Data Register */
+ #define EEDR (0x1D + __SFR_OFFSET)
+
+ /* EEPROM Address Register Low */
+ #define EEARL (0x1E + __SFR_OFFSET)
+
+ /* EEPROM Address Register High */
+ #define EEARH (0x1F + __SFR_OFFSET)
+
+ /* Special Function I/O Register */
+ #define SFIOR (0x20 + __SFR_OFFSET)
+
+ /* Watchdog Timer Control Register */
+ #define WDTCR (0x21 + __SFR_OFFSET)
+
+ /* On-chip Debug Register */
+ #define OCDR (0x22 + __SFR_OFFSET)
+
+ /* Timer2 Output Compare Register */
+ #define OCR2 (0x23 + __SFR_OFFSET)
+
+ /* Timer/Counter 2 */
+ #define TCNT2 (0x24 + __SFR_OFFSET)
+
+ /* Timer/Counter 2 Control register */
+ #define TCCR2 (0x25 + __SFR_OFFSET)
+
+ /* T/C 1 Input Capture Register Low */
+ #define ICR1L (0x26 + __SFR_OFFSET)
+
+ /* T/C 1 Input Capture Register High */
+ #define ICR1H (0x27 + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register B Low */
+ #define OCR1BL (0x28 + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register B High */
+ #define OCR1BH (0x29 + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register A Low */
+ #define OCR1AL (0x2A + __SFR_OFFSET)
+
+ /* Timer/Counter1 Output Compare Register A High */
+ #define OCR1AH (0x2B + __SFR_OFFSET)
+
+ /* Timer/Counter 1 Low */
+ #define TCNT1L (0x2C + __SFR_OFFSET)
+
+ /* Timer/Counter 1 High */
+ #define TCNT1H (0x2D + __SFR_OFFSET)
+
+ /* Timer/Counter 1 Control and Status Register */
+ #define TCCR1B (0x2E + __SFR_OFFSET)
+
+ /* Timer/Counter 1 Control Register */
+ #define TCCR1A (0x2F + __SFR_OFFSET)
+
+ /* Timer/Counter 0 Asynchronous Control & Status Register */
+ #define ASSR (0x30 + __SFR_OFFSET)
+
+ /* Output Compare Register 0 */
+ #define OCR0 (0x31 + __SFR_OFFSET)
+
+ /* Timer/Counter 0 */
+ #define TCNT0 (0x32 + __SFR_OFFSET)
+
+ /* Timer/Counter 0 Control Register */
+ #define TCCR0 (0x33 + __SFR_OFFSET)
+
+ /* MCU Status Register */
+ #define MCUSR (0x34 + __SFR_OFFSET)
+
+ /* MCU general Control Register */
+ #define MCUCR (0x35 + __SFR_OFFSET)
+
+ /* Timer/Counter Interrupt Flag Register */
+ #define TIFR (0x36 + __SFR_OFFSET)
+
+ /* Timer/Counter Interrupt MaSK register */
+ #define TIMSK (0x37 + __SFR_OFFSET)
+
+ /* External Interrupt Flag Register */
+ #define EIFR (0x38 + __SFR_OFFSET)
+
+ /* External Interrupt MaSK register */
+ #define EIMSK (0x39 + __SFR_OFFSET)
+
+ /* External Interrupt Control Register B */
+ #define EICRB (0x3A + __SFR_OFFSET)
+
+ /* RAM Page Z select register */
+ #define RAMPZ (0x3B + __SFR_OFFSET)
+
+ /* XDIV Divide control register */
+ #define XDIV (0x3C + __SFR_OFFSET)
+
+ /* Stack Pointer Low */
+ #define SPL (0x3D + __SFR_OFFSET)
+
+ /* Stack Pointer High */
+ #define SPH (0x3E + __SFR_OFFSET)
+
+ /* Status REGister */
+ #define SREG (0x3F + __SFR_OFFSET)
+
+ /* Data Direction Register, Port F */
+ #define DDRF (0x61)
+
+ /* Data Register, Port F */
+ #define PORTF (0x62)
+
+ /* Input Pins, Port G */
+ #define PING (0x63)
+
+ /* Data Direction Register, Port G */
+ #define DDRG (0x64)
+
+ /* Data Register, Port G */
+ #define PORTG (0x65)
+
+ /* Store Program Memory Control Register */
+ #define SPMCR (0x68)
+
+ /* External Interrupt Control Register A */
+ #define EICRA (0x6A)
+
+ /* External Memory Control Register B */
+ #define XMCRB (0x6C)
+
+ /* External Memory Control Register A */
+ #define XMCRA (0x6D)
+
+ /* Oscillator Calibration Register */
+ #define OSCCAL (0x6F)
+
+ /* 2-wire Serial Interface Bit Rate Register */
+ #define TWBR (0x70)
+
+ /* 2-wire Serial Interface Status Register */
+ #define TWSR (0x71)
+
+ /* 2-wire Serial Interface Address Register */
+ #define TWAR (0x72)
+
+ /* 2-wire Serial Interface Data Register */
+ #define TWDR (0x73)
+
+ /* 2-wire Serial Interface Control Register */
+ #define TWCR (0x74)
+
+ /* Time Counter 1 Output Compare Register C Low */
+ #define OCR1CL (0x78)
+
+ /* Time Counter 1 Output Compare Register C High */
+ #define OCR1CH (0x79)
+
+ /* Timer/Counter 1 Control Register C */
+ #define TCCR1C (0x7A)
+
+ /* Extended Timer Interrupt Flag Register */
+ #define ETIFR (0x7C)
+
+ /* Extended Timer Interrupt Mask Register */
+ #define ETIMSK (0x7D)
+
+ /* Timer/Counter 3 Input Capture Register Low */
+ #define ICR3L (0x80)
+
+ /* Timer/Counter 3 Input Capture Register High */
+ #define ICR3H (0x81)
+
+ /* Timer/Counter 3 Output Compare Register C Low */
+ #define OCR3CL (0x82)
+
+ /* Timer/Counter 3 Output Compare Register C High */
+ #define OCR3CH (0x83)
+
+ /* Timer/Counter 3 Output Compare Register B Low */
+ #define OCR3BL (0x84)
+
+ /* Timer/Counter 3 Output Compare Register B High */
+ #define OCR3BH (0x85)
+
+ /* Timer/Counter 3 Output Compare Register A Low */
+ #define OCR3AL (0x86)
+
+ /* Timer/Counter 3 Output Compare Register A High */
+ #define OCR3AH (0x87)
+
+ /* Timer/Counter 3 Counter Register High */
+ #define TCNT3L (0x88)
+
+ /* Timer/Counter 3 Counter Register High */
+ #define TCNT3H (0x89)
+
+ /* Timer/Counter 3 Control Register B */
+ #define TCCR3B (0x8A)
+
+ /* Timer/Counter 3 Control Register A */
+ #define TCCR3A (0x8B)
+
+ /* Timer/Counter 3 Control Register C */
+ #define TCCR3C (0x8C)
+
+ /* USART0 Baud Rate Register High */
+ #define UBRR0H (0x90)
+
+ /* USART0 Control and Status Register C */
+ #define UCSR0C (0x95)
+
+ /* USART1 Baud Rate Register High */
+ #define UBRR1H (0x98)
+
+ /* USART1 Baud Rate Register Low*/
+ #define UBRR1L (0x99)
+
+ /* USART1 Control and Status Register B */
+ #define UCSR1B (0x9A)
+
+ /* USART1 Control and Status Register A */
+ #define UCSR1A (0x9B)
+
+ /* USART1 I/O Data Register */
+ #define UDR1 (0x9C)
+
+ /*
+ * Interrupt Vector Definitions
+ */
+
+ #define SIG_INTERRUPT0 _vector_1
+ #define SIG_INTERRUPT1 _vector_2
+ #define SIG_INTERRUPT2 _vector_3
+ #define SIG_INTERRUPT3 _vector_4
+ #define SIG_INTERRUPT4 _vector_5
+ #define SIG_INTERRUPT5 _vector_6
+ #define SIG_INTERRUPT6 _vector_7
+ #define SIG_INTERRUPT7 _vector_8
+ #define SIG_OUTPUT_COMPARE2 _vector_9
+ #define SIG_OVERFLOW2 _vector_10
+ #define SIG_INPUT_CAPTURE1 _vector_11
+ #define SIG_OUTPUT_COMPARE1A _vector_12
+ #define SIG_OUTPUT_COMPARE1B _vector_13
+ #define SIG_OVERFLOW1 _vector_14
+ #define SIG_OUTPUT_COMPARE0 _vector_15
+ #define SIG_OVERFLOW0 _vector_16
+ #define SIG_SPI _vector_17
+ #define SIG_UART0_RECV _vector_18
+ #define SIG_UART0_DATA _vector_19
+ #define SIG_UART0_TRANS _vector_20
+ #define SIG_ADC _vector_21
+ #define SIG_EEPROM_READY _vector_22
+ #define SIG_COMPARATOR _vector_23
+ #define SIG_OUTPUT_COMPARE1C _vector_24
+ #define SIG_INPUT_CAPTURE3 _vector_25
+ #define SIG_OUTPUT_COMPARE3A _vector_26
+ #define SIG_OUTPUT_COMPARE3B _vector_27
+ #define SIG_OUTPUT_COMPARE3C _vector_28
+ #define SIG_OVERFLOW3 _vector_29
+ #define SIG_UART1_RECV _vector_30
+ #define SIG_UART1_DATA _vector_31
+ #define SIG_UART1_TRANS _vector_32
+ #define SIG_2WIRE_SERIAL _vector_33
+ #define SIG_SPM_READY _vector_34
+
+ #define END_VECTOR (34)
+ #define INT_VECT_SIZE (0x8a)
+
+ /*
+ The Register Bit names are represented by their bit number (0-7).
+ */
+
+ /* 2-wire Control Register */
+ #define TWINT 7
+ #define TWEA 6
+ #define TWSTA 5
+ #define TWSTO 4
+ #define TWWC 3
+ #define TWEN 2
+ #define TWIE 0
+
+ /* 2-wire Address Register */
+ #define TWA6 7
+ #define TWA5 6
+ #define TWA4 5
+ #define TWA3 4
+ #define TWA2 3
+ #define TWA1 2
+ #define TWA0 1
+ #define TWGCE 0
+
+ /* 2-wire Status Register */
+ #define TWS7 7
+ #define TWS6 6
+ #define TWS5 5
+ #define TWS4 4
+ #define TWS3 3
+ #define TWPS1 1
+ #define TWPS0 0
+
+ /* External Memory Control Register A */
+ #define SRL2 6
+ #define SRL1 5
+ #define SRL0 4
+ #define SRW01 3
+ #define SRW00 2
+ #define SRW11 1
+
+ /* External Memory Control Register B */
+ #define XMBK 7
+ #define XMM2 2
+ #define XMM1 1
+ #define XMM0 0
+
+ /* XDIV Divide control register*/
+ #define XDIVEN 7
+ #define XDIV6 6
+ #define XDIV5 5
+ #define XDIV4 4
+ #define XDIV3 3
+ #define XDIV2 2
+ #define XDIV1 1
+ #define XDIV0 0
+
+ /* RAM Page Z select register */
+ #define RAMPZ0 0
+
+ /* External Interrupt Control Register A */
+ #define ISC31 7
+ #define ISC30 6
+ #define ISC21 5
+ #define ISC20 4
+ #define ISC11 3
+ #define ISC10 2
+ #define ISC01 1
+ #define ISC00 0
+
+ /* External Interrupt Control Register B */
+ #define ISC71 7
+ #define ISC70 6
+ #define ISC61 5
+ #define ISC60 4
+ #define ISC51 3
+ #define ISC50 2
+ #define ISC41 1
+ #define ISC40 0
+
+ /* Store Program Memory Control Register */
+ #define SPMIE 7
+ #define RWWSB 6
+ #define RWWSRE 4
+ #define BLBSET 3
+ #define PGWRT 2
+ #define PGERS 1
+ #define SPMEN 0
+
+ /* External Interrupt MaSK register */
+ #define INT7 7
+ #define INT6 6
+ #define INT5 5
+ #define INT4 4
+ #define INT3 3
+ #define INT2 2
+ #define INT1 1
+ #define INT0 0
+
+ /* External Interrupt Flag Register */
+ #define INTF7 7
+ #define INTF6 6
+ #define INTF5 5
+ #define INTF4 4
+
+ /* Timer/Counter Interrupt MaSK register */
+ #define OCIE2 7
+ #define TOIE2 6
+ #define TICIE1 5
+ #define OCIE1A 4
+ #define OCIE1B 3
+ #define TOIE1 2
+ #define OCIE0 1
+ #define TOIE0 0
+
+ /* Timer/Counter Interrupt Flag Register */
+ #define OCF2 7
+ #define TOV2 6
+ #define ICF1 5
+ #define OCF1A 4
+ #define OCF1B 3
+ #define TOV1 2
+ #define OCF0 1
+ #define TOV0 0
+
+ /* Extended Timer Interrupt MaSK register */
+ #define TICIE3 5
+ #define OCIE3A 4
+ #define OCIE3B 3
+ #define TOIE3 2
+ #define OCIE3C 1
+ #define OCIE1C 0
+
+ /* Extended Timer Interrupt Flag Register */
+ #define ICF3 5
+ #define OCF3A 4
+ #define OCF3B 3
+ #define TOV3 2
+ #define OCF3C 1
+ #define OCF1C 0
+
+ /* MCU general Control Register */
+ #define SRE 7
+ #define SRW 6
+ #define SE 5
+ #define SM1 4
+ #define SM0 3
+ #define SM2 2
+ #define IVSEL 1
+ #define IVCE 0
+
+ /* MCU Status Register */
+ #define JTD 7
+ #define JTRF 4
+ #define WDRF 3
+ #define BORF 2
+ #define EXTRF 1
+ #define PORF 0
+
+ /* Timer/Counter Control Register */
+ #define FOC 7
+ #define WGM0 6
+ #define COM1 5
+ #define COM0 4
+ #define WGM1 3
+ #define CS2 2
+ #define CS1 1
+ #define CS0 0
+
+ /* Timer/Counter 0 Asynchronous Control & Status Register */
+ #define AS0 3
+ #define TCN0UB 2
+ #define OCR0UB 1
+ #define TCR0UB 0
+
+ /* Timer/Counter Control Register A */
+ #define COMA1 7
+ #define COMA0 6
+ #define COMB1 5
+ #define COMB0 4
+ #define COMC1 3
+ #define COMC0 2
+ #define WGMA1 1
+ #define WGMA0 0
+
+ /* Timer/Counter Control and Status Register B */
+ #define ICNC 7
+ #define ICES 6
+ #define WGMB3 4
+ #define WGMB2 3
+ #define CSB2 2
+ #define CSB1 1
+ #define CSB0 0
+
+ /* Timer/Counter Control Register C */
+ #define FOCA 7
+ #define FOCB 6
+ #define FOCC 5
+
+ /* On-chip Debug Register */
+ #define OCDR7 7
+ #define OCDR6 6
+ #define OCDR5 5
+ #define OCDR4 4
+ #define OCDR3 3
+ #define OCDR2 2
+ #define OCDR1 1
+ #define OCDR0 0
+
+ /* Watchdog Timer Control Register */
+ #define WDCE 4
+ #define WDE 3
+ #define WDP2 2
+ #define WDP1 1
+ #define WDP0 0
+
+ /* Special Function I/O Register */
+ #define TSM 7
+ #define ADHSM 4
+ #define ACME 3
+ #define PUD 2
+ #define PSR0 1
+ #define PSR321 0
+
+ /* EEPROM Control Register */
+ #define EERIE 3
+ #define EEMWE 2
+ #define EEWE 1
+ #define EERE 0
+
+ /* Port Data Register */
+ #define PORT7 7
+ #define PORT6 6
+ #define PORT5 5
+ #define PORT4 4
+ #define PORT3 3
+ #define PORT2 2
+ #define PORT1 1
+ #define PORT0 0
+
+ /* Port Data Direction Register */
+ #define DD7 7
+ #define DD6 6
+ #define DD5 5
+ #define DD4 4
+ #define DD3 3
+ #define DD2 2
+ #define DD1 1
+ #define DD0 0
+
+ /* Port Input Pins */
+ #define PIN7 7
+ #define PIN6 6
+ #define PIN5 5
+ #define PIN4 4
+ #define PIN3 3
+ #define PIN2 2
+ #define PIN1 1
+ #define PIN0 0
+
+ /* Status Register */
+ #define SREG_I 7
+ #define SREG_T 6
+ #define SREG_H 5
+ #define SREG_S 4
+ #define SREG_V 3
+ #define SREG_N 2
+ #define SREG_Z 1
+ #define SREG_C 0
+
+ /* SPI Status Register */
+ #define SPIF 7
+ #define WCOL 6
+ #define SPI2X 0
+
+ /* SPI Control Register */
+ #define SPIE 7
+ #define SPE 6
+ #define DORD 5
+ #define MSTR 4
+ #define CPOL 3
+ #define CPHA 2
+ #define SPR1 1
+ #define SPR0 0
+
+ /* USART Register C */
+ #define UMSEL 6
+ #define UPM1 5
+ #define UPM0 4
+ #define USBS 3
+ #define UCSZ1 2
+ #define UCSZ0 1
+ #define UCPOL 0
+
+ /* USART Status Register A */
+ #define RXC 7
+ #define TXC 6
+ #define UDRE 5
+ #define FE 4
+ #define OVR 3 /* This definition differs from the databook */
+ /*definition to avoid problems with the OR instruction */
+
+ /* USART Control Register */
+ #define RXCIE 7
+ #define TXCIE 6
+ #define UDRIE 5
+ #define RXEN 4
+ #define TXEN 3
+ #define UCSZ 2
+ #define RXB8 1
+ #define TXB8 0
+
+ /* Analog Comparator Control and Status Register */
+ #define ACD 7
+ #define ACBG 6
+ #define ACO 5
+ #define ACI 4
+ #define ACIE 3
+ #define ACIC 2
+ #define ACIS1 1
+ #define ACIS0 0
+
+ /* ADC Control and status register */
+ #define ADEN 7
+ #define ADSC 6
+ #define ADFR 5
+ #define ADIF 4
+ #define ADIE 3
+ #define ADPS2 2
+ #define ADPS1 1
+ #define ADPS0 0
+
+ /* ADC Multiplexer select */
+ #define REFS1 7
+ #define REFS0 6
+ #define ADLAR 5
+ #define MUX4 4
+ #define MUX3 3
+ #define MUX2 2
+ #define MUX1 1
+ #define MUX0 0
+
+ /* Pointer definition */
+ #define XL r26
+ #define XH r27
+ #define YL r28
+ #define YH r29
+ #define ZL r30
+ #define ZH r31
+
+ /* Constants */
+ #define RAMEND 0x10FF /* Last On-Chip SRAM Location */
+ #define XRAMEND 0xFFFF
+ #define E2END 0x0FFF
+ #define FLASHEND 0x1FFFF
+
+ #endif /* __IOM128 */
diff -rc3P avr-libc-20011029/include/iom161.h
avr-libc-20011029-patch-0.2/include/iom161.h
*** avr-libc-20011029/include/iom161.h Sun Oct 29 04:17:54 2000
--- avr-libc-20011029-patch-0.2/include/iom161.h Mon Nov 19 14:57:00 2001
***************
*** 213,240 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x04)
! #define INT1_vect (0x08)
! #define INT2_vect (0x0C)
! #define TIMER2_COMP_vect (0x10)
! #define TIMER2_OVF_vect (0x14)
! #define TIMER1_CAPT_vect (0x18)
! #define TIMER1_COMPA_vect (0x1C)
! #define TIMER1_COMPB_vect (0x20)
! #define TIMER1_OVF_vect (0x24)
! #define TIMER0_COMP_vect (0x28)
! #define TIMER0_OVF_vect (0x2C)
! #define SPI_STC_vect (0x30)
! #define UART_RX_vect (0x34)
! #define UART1_RX_vect (0x38)
! #define UART_UDRE_vect (0x3C)
! #define UART1_UDRE_vect (0x40)
! #define UART_TX_vect (0x44)
! #define UART1_TX_vect (0x48)
! #define EE_RDY_vect (0x4C)
! #define ANA_COMP_vect (0x50)
#define INT_VECT_SIZE (0x54)
/* Bit numbers */
--- 213,240 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INTERRUPT2 _vector_3
! #define SIG_OUTPUT_COMPARE2 _vector_4
! #define SIG_OVERFLOW2 _vector_5
! #define SIG_INPUT_CAPTURE1 _vector_6
! #define SIG_OUTPUT_COMPARE1A _vector_7
! #define SIG_OUTPUT_COMPARE1B _vector_8
! #define SIG_OVERFLOW1 _vector_9
! #define SIG_OUTPUT_COMPARE0 _vector_10
! #define SIG_OVERFLOW0 _vector_11
! #define SIG_SPI _vector_12
! #define SIG_UART0_RECV _vector_13
! #define SIG_UART1_RECV _vector_14
! #define SIG_UART0_DATA _vector_15
! #define SIG_UART1_DATA _vector_16
! #define SIG_UART0_TRANS _vector_17
! #define SIG_UART1_TRANS _vector_18
! #define SIG_EEPROM_READY _vector_19
! #define SIG_COMPARATOR _vector_20
+ #define END_VECTOR (20)
#define INT_VECT_SIZE (0x54)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iom163.h
avr-libc-20011029-patch-0.2/include/iom163.h
*** avr-libc-20011029/include/iom163.h Sun Nov 19 01:02:01 2000
--- avr-libc-20011029-patch-0.2/include/iom163.h Mon Nov 19 14:57:38 2001
***************
*** 129,153 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x04)
! #define INT1_vect (0x08)
! #define TIMER2_COMP_vect (0x0C)
! #define TIMER2_OVF_vect (0x10)
! #define TIMER1_CAPT_vect (0x14)
! #define TIMER1_COMPA_vect (0x18)
! #define TIMER1_COMPB_vect (0x1C)
! #define TIMER1_OVF_vect (0x20)
! #define TIMER0_OVF_vect (0x24)
! #define SPI_STC_vect (0x28)
! #define UART_RX_vect (0x2C)
! #define UART_UDRE_vect (0x30)
! #define UART_TX_vect (0x34)
! #define ADC_vect (0x38)
! #define EE_RDY_vect (0x3C)
! #define ANA_COMP_vect (0x40)
! #define TWI_INT_vect (0x44)
#define INT_VECT_SIZE (0x48)
/* Bit numbers */
--- 129,152 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_OUTPUT_COMPARE2 _vector_3
! #define SIG_OVERFLOW2 _vector_4
! #define SIG_INPUT_CAPTURE1 _vector_5
! #define SIG_OUTPUT_COMPARE1A _vector_6
! #define SIG_OUTPUT_COMPARE1B _vector_7
! #define SIG_OVERFLOW1 _vector_8
! #define SIG_OVERFLOW0 _vector_9
! #define SIG_SPI _vector_10
! #define SIG_UART_RECV _vector_11
! #define SIG_UART_DATA _vector_12
! #define SIG_UART_TRANS _vector_13
! #define SIG_ADC _vector_14
! #define SIG_EEPROM_READY _vector_15
! #define SIG_2WIRE_SERIAL _vector_16
+ #define END_VECTOR (16)
#define INT_VECT_SIZE (0x48)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iom32.h
avr-libc-20011029-patch-0.2/include/iom32.h
*** avr-libc-20011029/include/iom32.h Sun Oct 29 04:23:54 2000
--- avr-libc-20011029-patch-0.2/include/iom32.h Mon Nov 19 14:59:01 2001
***************
*** 136,162 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x04)
! #define INT1_vect (0x08)
! #define INT2_vect (0x0C)
! #define TIMER2_COMP_vect (0x10)
! #define TIMER2_OVF_vect (0x14)
! #define TIMER1_CAPT_vect (0x18)
! #define TIMER1_COMPA_vect (0x1C)
! #define TIMER1_COMPB_vect (0x20)
! #define TIMER1_OVF_vect (0x24)
! #define TIMER0_COMP_vect (0x28)
! #define TIMER0_OVF_vect (0x2C)
! #define SPI_STC_vect (0x30)
! #define UART_RX_vect (0x34)
! #define UART_UDRE_vect (0x38)
! #define UART_TX_vect (0x3C)
! #define ADC_vect (0x40)
! #define EE_RDY_vect (0x44)
! #define ANA_COMP_vect (0x48)
! #define TWI_INT_vect (0x4C)
#define INT_VECT_SIZE (0x50)
/* Bit numbers */
--- 136,162 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INTERRUPT3 _vector_3
! #define SIG_OUTPUT_COMPARE2 _vector_4
! #define SIG_OVERFLOW2 _vector_5
! #define SIG_INPUT_CAPTURE1 _vector_6
! #define SIG_OUTPUT_COMPARE1A _vector_7
! #define SIG_OUTPUT_COMPARE1B _vector_8
! #define SIG_OVERFLOW1 _vector_9
! #define SIG_OUTPUT_COMPARE0 _vector_10
! #define SIG_OVERFLOW0 _vector_11
! #define SIG_SPI _vector_12
! #define SIG_UART_RECV _vector_13
! #define SIG_UART_DATA _vector_14
! #define SIG_UART_TRANS _vector_15
! #define SIG_ADC _vector_16
! #define SIG_EEPROM_READY _vector_17
! #define SIG_COMPARATOR _vector_18
! #define SIG_2WIRE_SERIAL _vector_19
+ #define END_VECTOR (19)
#define INT_VECT_SIZE (0x50)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iom603.h
avr-libc-20011029-patch-0.2/include/iom603.h
*** avr-libc-20011029/include/iom603.h Fri Jul 21 16:20:57 2000
--- avr-libc-20011029-patch-0.2/include/iom603.h Mon Nov 19 14:59:13 2001
***************
*** 183,215 ****
/* Interrupt Vector Definitions */
/*==============================*/
! /* NB! vectors are specified as byte addresses */
!
! #define RESET_vect (0x00)
! #define INT0_vect (0x04)
! #define INT1_vect (0x08)
! #define INT2_vect (0x0C)
! #define INT3_vect (0x10)
! #define INT4_vect (0x14)
! #define INT5_vect (0x18)
! #define INT6_vect (0x1C)
! #define INT7_vect (0x20)
! #define TIMER2_COMP_vect (0x24)
! #define TIMER2_OVF_vect (0x28)
! #define TIMER1_CAPT_vect (0x2C)
! #define TIMER1_COMPA_vect (0x30)
! #define TIMER1_COMPB_vect (0x34)
! #define TIMER1_OVF_vect (0x38)
! #define TIMER0_COMP_vect (0x3C)
! #define TIMER0_OVF_vect (0x40)
! #define SPI_STC_vect (0x44)
! #define UART_RX_vect (0x48)
! #define UART_UDRE_vect (0x4C)
! #define UART_TX_vect (0x50)
! #define ADC_vect (0x54)
! #define EE_RDY_vect (0x58)
! #define ANA_COMP_vect (0x5C)
#define INT_VECT_SIZE (0x60)
/*
--- 183,213 ----
/* Interrupt Vector Definitions */
/*==============================*/
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_INTERRUPT2 _vector_3
! #define SIG_INTERRUPT3 _vector_4
! #define SIG_INTERRUPT4 _vector_5
! #define SIG_INTERRUPT5 _vector_6
! #define SIG_INTERRUPT6 _vector_7
! #define SIG_INTERRUPT7 _vector_8
! #define SIG_OUTPUT_COMPARE2 _vector_9
! #define SIG_OVERFLOW2 _vector_10
! #define SIG_INPUT_CAPTURE1 _vector_11
! #define SIG_OUTPUT_COMPARE1A _vector_12
! #define SIG_OUTPUT_COMPARE1B _vector_13
! #define SIG_OVERFLOW1 _vector_14
! #define SIG_OUTPUT_COMPARE0 _vector_15
! #define SIG_OVERFLOW0 _vector_16
! #define SIG_SPI _vector_17
! #define SIG_UART_RECV _vector_18
! #define SIG_UART_DATA _vector_19
! #define SIG_UART_TRANS _vector_20
! #define SIG_ADC _vector_21
! #define SIG_EEPROM_READY _vector_22
! #define SIG_COMPARATOR _vector_23
+ #define END_VECTOR (23)
#define INT_VECT_SIZE (0x60)
/*
diff -rc3P avr-libc-20011029/include/iom83.h
avr-libc-20011029-patch-0.2/include/iom83.h
*** avr-libc-20011029/include/iom83.h Sun Oct 29 04:24:38 2000
--- avr-libc-20011029-patch-0.2/include/iom83.h Mon Nov 19 14:59:26 2001
***************
*** 130,154 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define TIMER2_COMP_vect (0x06)
! #define TIMER2_OVF_vect (0x08)
! #define TIMER1_CAPT_vect (0x0A)
! #define TIMER1_COMPA_vect (0x0C)
! #define TIMER1_COMPB_vect (0x0E)
! #define TIMER1_OVF_vect (0x10)
! #define TIMER0_OVF_vect (0x12)
! #define SPI_STC_vect (0x14)
! #define UART_RX_vect (0x16)
! #define UART_UDRE_vect (0x18)
! #define UART_TX_vect (0x1A)
! #define ADC_vect (0x1C)
! #define EE_RDY_vect (0x1E)
! #define ANA_COMP_vect (0x20)
! #define TWI_INT_vect (0x22)
#define INT_VECT_SIZE (0x24)
/* Bit numbers */
--- 130,154 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_OUTPUT_COMPARE2 _vector_3
! #define SIG_OVERFLOW2 _vector_4
! #define SIG_INPUT_CAPTURE1 _vector_5
! #define SIG_OUTPUT_COMPARE1A _vector_6
! #define SIG_OUTPUT_COMPARE1B _vector_7
! #define SIG_OVERFLOW1 _vector_8
! #define SIG_OVERFLOW0 _vector_9
! #define SIG_SPI _vector_10
! #define SIG_UART_RECV _vector_11
! #define SIG_UART_DATA _vector_12
! #define SIG_UART_TRANS _vector_13
! #define SIG_ADC _vector_14
! #define SIG_EEPROM_READY _vector_15
! #define SIG_COMPARATOR _vector_16
! #define SIG_2WIRE_SERIAL _vector_17
+ #define END_VECTOR (17)
#define INT_VECT_SIZE (0x24)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iomacros.h
avr-libc-20011029-patch-0.2/include/iomacros.h
*** avr-libc-20011029/include/iomacros.h Sun Jul 8 04:08:41 2001
--- avr-libc-20011029-patch-0.2/include/iomacros.h Fri Nov 16 16:56:57 2001
***************
*** 24,32 ****
#define BV(x) (1 << (x))
#endif
/* Memory mapped I/O - use for non-constant I/O space addresses. */
! #define __mmio(port) (*((volatile uint8_t *)((uint8_t)(port) + 0x20)))
/* Macros for access to 8-bit I/O registers with constant address. */
--- 24,36 ----
#define BV(x) (1 << (x))
#endif
+ #ifndef __SFR_OFFSET
+ #define __SFR_OFFSET 0
+ #endif /* !__SFR_OFFSET */
+
/* Memory mapped I/O - use for non-constant I/O space addresses. */
! #define __mmio(port) (*((volatile uint8_t *)((uint8_t)(port-__SFR_OFFSET) +
0x20)))
/* Macros for access to 8-bit I/O registers with constant address. */
***************
*** 35,41 ****
__asm__ __volatile__ ( \
"in %0,%1" \
: "=r" (__t) \
! : "I" ((uint8_t)(port)) \
); \
__t; \
})
--- 39,45 ----
__asm__ __volatile__ ( \
"in %0,%1" \
: "=r" (__t) \
! : "I" ((uint8_t)(port-__SFR_OFFSET)) \
); \
__t; \
})
***************
*** 49,62 ****
"out %1,%0" \
: /* no outputs */ \
: "r" ((uint8_t)(val)), \
! "I" ((uint8_t)(port)) \
)
#define __outb_zero(port) \
__asm__ __volatile__ ( \
"out %0,__zero_reg__" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)) \
)
/* Macros for access to 8-bit I/O registers (auto detect const address). */
--- 53,66 ----
"out %1,%0" \
: /* no outputs */ \
: "r" ((uint8_t)(val)), \
! "I" ((uint8_t)(port-__SFR_OFFSET)) \
)
#define __outb_zero(port) \
__asm__ __volatile__ ( \
"out %0,__zero_reg__" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)) \
)
/* Macros for access to 8-bit I/O registers (auto detect const address). */
***************
*** 86,92 ****
"in %A0,%1" "\n\t" \
"in %B0,(%1)+1" \
: "=r" (__t) \
! : "I" ((uint8_t)(port)) \
); \
__t; \
})
--- 90,96 ----
"in %A0,%1" "\n\t" \
"in %B0,(%1)+1" \
: "=r" (__t) \
! : "I" ((uint8_t)(port-__SFR_OFFSET)) \
); \
__t; \
})
***************
*** 100,106 ****
"out __SREG__,__tmp_reg__" "\n\t" \
"in %B0,(%1)+1" \
: "=r" (__t) \
! : "I" ((uint8_t)(port)) \
: "r0" \
); \
__t; \
--- 104,110 ----
"out __SREG__,__tmp_reg__" "\n\t" \
"in %B0,(%1)+1" \
: "=r" (__t) \
! : "I" ((uint8_t)(port-__SFR_OFFSET)) \
: "r0" \
); \
__t; \
***************
*** 112,118 ****
"out %1,%A0" \
: /* no outputs */ \
: "r" ((uint16_t)(val)), \
! "I" ((uint8_t)(port)) \
)
#define __outw_atomic(val, port) \
--- 116,122 ----
"out %1,%A0" \
: /* no outputs */ \
: "r" ((uint16_t)(val)), \
! "I" ((uint8_t)(port-__SFR_OFFSET)) \
)
#define __outw_atomic(val, port) \
***************
*** 124,140 ****
"out %1,%A0" \
: /* no outputs */ \
: "r" ((uint16_t)(val)), \
! "I" ((uint8_t)(port)) \
: "r0" \
)
! /* __cbi / __sbi require constant port < 0x20 and constant bit */
#define __cbi(port, bit) \
__asm__ __volatile__ ( \
"cbi %0,%1" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)), \
"I" ((uint8_t)(bit)) \
)
--- 128,144 ----
"out %1,%A0" \
: /* no outputs */ \
: "r" ((uint16_t)(val)), \
! "I" ((uint8_t)(port-__SFR_OFFSET)) \
: "r0" \
)
! /* __cbi / __sbi require constant port-__SFR_OFFSET < 0x20 and constant bit */
#define __cbi(port, bit) \
__asm__ __volatile__ ( \
"cbi %0,%1" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"I" ((uint8_t)(bit)) \
)
***************
*** 142,148 ****
__asm__ __volatile__ ( \
"sbi %0,%1" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)), \
"I" ((uint8_t)(bit)) \
)
--- 146,152 ----
__asm__ __volatile__ ( \
"sbi %0,%1" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"I" ((uint8_t)(bit)) \
)
***************
*** 154,160 ****
"and __tmp_reg__,%1" "\n\t" \
"out %0,__tmp_reg__" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)), \
"r" ((uint8_t)(val)) \
: "r0" \
)
--- 158,164 ----
"and __tmp_reg__,%1" "\n\t" \
"out %0,__tmp_reg__" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"r" ((uint8_t)(val)) \
: "r0" \
)
***************
*** 165,171 ****
"or __tmp_reg__,%1" "\n\t" \
"out %0,__tmp_reg__" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)), \
"r" ((uint8_t)(val)) \
: "r0" \
)
--- 169,175 ----
"or __tmp_reg__,%1" "\n\t" \
"out %0,__tmp_reg__" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"r" ((uint8_t)(val)) \
: "r0" \
)
***************
*** 217,223 ****
"sbis %1,%2" "\n\t" \
"inc %0" \
: "=r" (__t) \
! : "I" ((uint8_t)(port)), \
"I" ((uint8_t)(bit)) \
); \
__t; \
--- 221,227 ----
"sbis %1,%2" "\n\t" \
"inc %0" \
: "=r" (__t) \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"I" ((uint8_t)(bit)) \
); \
__t; \
***************
*** 230,236 ****
"sbic %1,%2" "\n\t" \
"inc %0" \
: "=r" (__t) \
! : "I" ((uint8_t)(port)), \
"I" ((uint8_t)(bit)) \
); \
__t; \
--- 234,240 ----
"sbic %1,%2" "\n\t" \
"inc %0" \
: "=r" (__t) \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"I" ((uint8_t)(bit)) \
); \
__t; \
***************
*** 243,249 ****
"L_%=: " "sbis %0,%1" "\n\t" \
"rjmp L_%=" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)), \
"I" ((uint8_t)(bit)) \
)
--- 247,253 ----
"L_%=: " "sbis %0,%1" "\n\t" \
"rjmp L_%=" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"I" ((uint8_t)(bit)) \
)
***************
*** 252,258 ****
"L_%=: " "sbic %0,%1" "\n\t" \
"rjmp L_%=" \
: /* no outputs */ \
! : "I" ((uint8_t)(port)), \
"I" ((uint8_t)(bit)) \
)
--- 256,262 ----
"L_%=: " "sbic %0,%1" "\n\t" \
"rjmp L_%=" \
: /* no outputs */ \
! : "I" ((uint8_t)(port-__SFR_OFFSET)), \
"I" ((uint8_t)(bit)) \
)
diff -rc3P avr-libc-20011029/include/iotn11.h
avr-libc-20011029-patch-0.2/include/iotn11.h
*** avr-libc-20011029/include/iotn11.h Sun Oct 29 04:26:19 2000
--- avr-libc-20011029-patch-0.2/include/iotn11.h Mon Nov 19 14:59:44 2001
***************
*** 83,95 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define PIN_vect (0x04)
! #define TIMER0_OVF_vect (0x06)
! #define ANA_COMP_vect (0x08)
! #define INT_VECT_SIZE (0x0A)
/* Bit numbers */
--- 83,95 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_PIN _vector_2
! #define SIG_OVERFLOW0 _vector_3
! #define SIG_COMPARATOR _vector_4
! #define END_VECTOR (5)
! #define INT_VECT_SIZE (0x0a)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iotn12.h
avr-libc-20011029-patch-0.2/include/iotn12.h
*** avr-libc-20011029/include/iotn12.h Sun Oct 29 04:26:41 2000
--- avr-libc-20011029-patch-0.2/include/iotn12.h Mon Nov 19 14:59:55 2001
***************
*** 96,109 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define PIN_vect (0x04)
! #define TIMER0_OVF_vect (0x06)
! #define EE_RDY_vect (0x08)
! #define ANA_COMP_vect (0x0A)
! #define INT_VECT_SIZE (0x0C)
/* Bit numbers */
--- 96,109 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_PIN _vector_2
! #define SIG_OVERFLOW0 _vector_3
! #define SIG_EEPROM_READY _vector_4
! #define SIG_COMPARATOR _vector_5
! #define END_VECTOR (5)
! #define INT_VECT_SIZE (0x0c)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iotn15.h
avr-libc-20011029-patch-0.2/include/iotn15.h
*** avr-libc-20011029/include/iotn15.h Sun Apr 1 01:56:44 2001
--- avr-libc-20011029-patch-0.2/include/iotn15.h Mon Nov 19 15:00:08 2001
***************
*** 106,122 ****
#define SREG 0x3F
/* Interrupt vectors (byte addresses) */
- /* Warning: different order (ADC is before EE_RDY in other devices) */
- #define RESET_vect (0x00)
- #define INT0_vect (0x02)
- #define PIN_vect (0x04)
- #define TIMER1_COMPA_vect (0x06)
- #define TIMER1_OVF_vect (0x08)
- #define TIMER0_OVF_vect (0x0A)
- #define EE_RDY_vect (0x0C)
- #define ANA_COMP_vect (0x0E)
- #define ADC_vect (0x10)
#define INT_VECT_SIZE (0x12)
/* Bit numbers */
--- 106,122 ----
#define SREG 0x3F
/* Interrupt vectors (byte addresses) */
+ #define SIG_INTERRUPT0 _vector_1
+ #define SIG_PIN _vector_2
+ #define SIG_OUTPUT_COMPARE1A _vector_3
+ #define SIG_OVERFLOW1 _vector_4
+ #define SIG_OVERFLOW0 _vector_5
+ #define SIG_EEPROM_READY _vector_6
+ #define SIG_COMPARATOR _vector_7
+ #define SIG_ADC _vector_8
+
+ #define END_VECTOR (9)
#define INT_VECT_SIZE (0x12)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/iotn22.h
avr-libc-20011029-patch-0.2/include/iotn22.h
*** avr-libc-20011029/include/iotn22.h Wed Jul 19 20:53:48 2000
--- avr-libc-20011029-patch-0.2/include/iotn22.h Mon Nov 19 15:00:29 2001
***************
*** 69,78 ****
/* NB! vectors are specified as byte addresses */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define TIMER0_OVF_vect (0x04)
#define INT_VECT_SIZE (0x06)
/*
--- 69,78 ----
/* NB! vectors are specified as byte addresses */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_OVERFLOW0 _vector_2
+ #define END_VECTOR (2)
#define INT_VECT_SIZE (0x06)
/*
diff -rc3P avr-libc-20011029/include/iotn28.h
avr-libc-20011029-patch-0.2/include/iotn28.h
*** avr-libc-20011029/include/iotn28.h Sun Oct 29 04:27:21 2000
--- avr-libc-20011029-patch-0.2/include/iotn28.h Mon Nov 19 15:00:47 2001
***************
*** 64,77 ****
/* Interrupt vectors (byte addresses) */
! #define RESET_vect (0x00)
! #define INT0_vect (0x02)
! #define INT1_vect (0x04)
! #define PIN_vect (0x06)
! #define TIMER0_OVF_vect (0x08)
! #define ANA_COMP_vect (0x0A)
! #define INT_VECT_SIZE (0x0C)
/* Bit numbers */
--- 64,77 ----
/* Interrupt vectors (byte addresses) */
! #define SIG_INTERRUPT0 _vector_1
! #define SIG_INTERRUPT1 _vector_2
! #define SIG_PIN _vector_3
! #define SIG_OVERFLOW0 _vector_4
! #define SIG_COMPARATOR _vector_5
! #define END_VECTOR (5)
! #define INT_VECT_SIZE (0x0c)
/* Bit numbers */
diff -rc3P avr-libc-20011029/include/math.h
avr-libc-20011029-patch-0.2/include/math.h
*** avr-libc-20011029/include/math.h Mon Aug 20 23:24:30 2001
--- avr-libc-20011029-patch-0.2/include/math.h Wed Nov 7 17:37:59 2001
***************
*** 19,24 ****
--- 19,28 ----
#define __ATTR_CONST__ __attribute__((__const__))
#endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
extern double cos(double) __ATTR_CONST__;
extern double fabs(double) __ATTR_CONST__;
#if 0
***************
*** 56,60 ****
--- 60,68 ----
extern double square(double) __ATTR_CONST__;
extern double inverse(double) __ATTR_CONST__;
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* _MATH_H */
diff -rc3P avr-libc-20011029/include/pgmspace.h
avr-libc-20011029-patch-0.2/include/pgmspace.h
*** avr-libc-20011029/include/pgmspace.h Sun Jul 1 23:52:36 2001
--- avr-libc-20011029-patch-0.2/include/pgmspace.h Wed Nov 7 17:39:46 2001
***************
*** 44,49 ****
--- 44,53 ----
#define PROGMEM __ATTR_PROGMEM__
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
typedef void prog_void PROGMEM;
typedef char prog_char PROGMEM;
typedef unsigned char prog_uchar PROGMEM;
***************
*** 110,114 ****
--- 114,122 ----
extern PGM_P strerror_P(int);
#endif
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* __PGMSPACE_H_ */
diff -rc3P avr-libc-20011029/include/sig-avr.h
avr-libc-20011029-patch-0.2/include/sig-avr.h
*** avr-libc-20011029/include/sig-avr.h Wed May 3 22:13:09 2000
--- avr-libc-20011029-patch-0.2/include/sig-avr.h Fri Nov 16 16:43:25 2001
***************
*** 3,92 ****
#ifndef _SIG_AVR_H_
#define _SIG_AVR_H_
! /* External Interrupt0 Function name */
! #define SIG_INTERRUPT0 _interrupt0_
!
! /* External Interrupt1 Function name */
! #define SIG_INTERRUPT1 _interrupt1_
!
! /* External Interrupt2 Function name (ATmega) */
! #define SIG_INTERRUPT2 _interrupt2_
!
! /* External Interrupt3 Function name (ATmega[16]03)*/
! #define SIG_INTERRUPT3 _interrupt3_
!
! /* External Interrupt4 Function name (ATmega[16]03) */
! #define SIG_INTERRUPT4 _interrupt4_
!
! /* External Interrupt5 Function name (ATmega[16]03) */
! #define SIG_INTERRUPT5 _interrupt5_
!
! /* External Interrupt6 Function name (ATmega[16]03) */
! #define SIG_INTERRUPT6 _interrupt6_
!
! /* External Interrupt7 Function name (ATmega[16]03) */
! #define SIG_INTERRUPT7 _interrupt7_
!
! /* Output Compare2 Interrupt Function name */
! #define SIG_OUTPUT_COMPARE2 _output_compare2_
!
! /* Overflow2 Interrupt Function name */
! #define SIG_OVERFLOW2 _overflow2_
!
! /* Input Capture1 Interrupt Function name */
! #define SIG_INPUT_CAPTURE1 _input_capture1_
!
! /* Output Compare1(A) Interrupt Function name */
! #define SIG_OUTPUT_COMPARE1A _output_compare1a_
!
! /* Output Compare1B Interrupt Function name */
! #define SIG_OUTPUT_COMPARE1B _output_compare1b_
!
! /* Overflow1 Interrupt Function name */
! #define SIG_OVERFLOW1 _overflow1_
!
! /* Output Compare0 Interrupt Function name */
! #define SIG_OUTPUT_COMPARE0 _output_compare0_
!
! /* Overflow0 Interrupt Function name */
! #define SIG_OVERFLOW0 _overflow0_
!
! /* SPI Interrupt Function name */
! #define SIG_SPI _spi_
!
! /* UART(0) Receive Complete Interrupt Function name */
! #define SIG_UART_RECV _uart_recv_
!
! /* UART1 Receive Complete Interrupt Function name (ATmega161) */
! #define SIG_UART1_RECV _uart1_recv_
!
! /* UART(0) Data Register Empty Interrupt Function name */
! #define SIG_UART_DATA _uart_data_
!
! /* UART1 Data Register Empty Interrupt Function name (ATmega161) */
! #define SIG_UART1_DATA _uart1_data_
!
! /* UART(0) Transmit Complete Interrupt Function name */
! #define SIG_UART_TRANS _uart_trans_
!
! /* UART1 Transmit Complete Interrupt Function name (ATmega161) */
! #define SIG_UART1_TRANS _uart1_trans_
!
! /* ADC Conversion complete */
! #define SIG_ADC _adc_
!
! /* Eeprom ready */
! #define SIG_EEPROM _eeprom_ready_
!
! /* Analog Comparator Interrupt Function name */
! #define SIG_COMPARATOR _comparator_
!
#define SIGNAL(signame) \
void signame (void) __attribute__ ((signal)); \
void signame (void)
#define INTERRUPT(signame) \
void signame (void) __attribute__ ((interrupt)); \
void signame (void)
#endif /* _SIG_AVR_H_ */
--- 3,28 ----
#ifndef _SIG_AVR_H_
#define _SIG_AVR_H_
! #ifdef __cplusplus
! #define SIGNAL(signame) \
! extern "C" void signame(void); \
! void signame (void) __attribute__ ((signal)); \
! void signame (void)
! #else
#define SIGNAL(signame) \
void signame (void) __attribute__ ((signal)); \
void signame (void)
+ #endif
+ #ifdef __cplusplus
+ #define INTERRUPT(signame) \
+ extern "C" void signame(void); \
+ void signame (void) __attribute__ ((interrupt)); \
+ void signame (void)
+ #else
#define INTERRUPT(signame) \
void signame (void) __attribute__ ((interrupt)); \
void signame (void)
+ #endif
#endif /* _SIG_AVR_H_ */
diff -rc3P avr-libc-20011029/include/stdlib.h
avr-libc-20011029-patch-0.2/include/stdlib.h
*** avr-libc-20011029/include/stdlib.h Sun Jul 8 04:51:27 2001
--- avr-libc-20011029-patch-0.2/include/stdlib.h Wed Nov 7 17:36:18 2001
***************
*** 10,15 ****
--- 10,19 ----
#define __ptr_t void *
#endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
typedef struct {
int quot;
int rem;
***************
*** 112,115 ****
--- 116,123 ----
extern void srand(unsigned int);
#endif
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* _STDLIB_H_ */
diff -rc3P avr-libc-20011029/include/string-avr.h
avr-libc-20011029-patch-0.2/include/string-avr.h
*** avr-libc-20011029/include/string-avr.h Sat Apr 1 23:07:05 2000
--- avr-libc-20011029-patch-0.2/include/string-avr.h Wed Nov 7 17:45:51 2001
***************
*** 36,41 ****
--- 36,45 ----
#define __const const
#define __string_h_int__ char
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
/* Copy N bytes of SRC to DEST. */
extern inline __ptr_t memcpy(__ptr_t __to, const void *__from, size_t __n)
{
***************
*** 361,366 ****
--- 365,374 ----
return __end ? __end - __string : __maxlen;
}
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* string-avr.h */
diff -rc3P avr-libc-20011029/include/string.h
avr-libc-20011029-patch-0.2/include/string.h
*** avr-libc-20011029/include/string.h Sun Jul 1 23:18:11 2001
--- avr-libc-20011029-patch-0.2/include/string.h Wed Nov 7 17:35:44 2001
***************
*** 26,31 ****
--- 26,35 ----
#define __ATTR_PURE__ __attribute__((__pure__))
#endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
extern void *memccpy(void *, const void *, int, size_t);
extern void *memchr(const void *, int, size_t) __ATTR_PURE__;
extern int memcmp(const void *, const void *, size_t) __ATTR_PURE__;
***************
*** 49,53 ****
--- 53,61 ----
extern char *strstr(const char *, const char *) __ATTR_PURE__;
extern char *strupr(char *);
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* _STRING_H_ */
diff -rc3P avr-libc-20011029/include/timer.h
avr-libc-20011029-patch-0.2/include/timer.h
*** avr-libc-20011029/include/timer.h Sat Apr 1 23:07:05 2000
--- avr-libc-20011029-patch-0.2/include/timer.h Wed Nov 7 17:44:33 2001
***************
*** 3,8 ****
--- 3,12 ----
#include <io.h>
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
enum {
STOP = 0,
CK = 1,
***************
*** 29,32 ****
--- 33,40 ----
outb (0x1, TCNT0);
}
+ #ifdef __cplusplus
+ }
+ #endif
+
#endif /* _TIMER_H_ */
diff -rc3P avr-libc-20011029/src/Makefile
avr-libc-20011029-patch-0.2/src/Makefile
*** avr-libc-20011029/src/Makefile Tue Oct 30 02:11:25 2001
--- avr-libc-20011029-patch-0.2/src/Makefile Fri Nov 16 16:54:02 2001
***************
*** 92,98 ****
crt_avr4_mega = crtm83.o # crtm85.o
! crt_avr5_mega = crtm161.o crtm163.o crtm32.o
crt_avr5_other = crtat94k.o
--- 92,98 ----
crt_avr4_mega = crtm83.o # crtm85.o
! crt_avr5_mega = crtm161.o crtm163.o crtm32.o crtm128.o
crt_avr5_other = crtat94k.o
diff -rc3P avr-libc-20011029/src/gcrt1.S avr-libc-20011029-patch-0.2/src/gcrt1.S
*** avr-libc-20011029/src/gcrt1.S Sun Oct 29 05:43:32 2000
--- avr-libc-20011029-patch-0.2/src/gcrt1.S Tue Nov 20 12:40:11 2001
***************
*** 36,43 ****
.extern __bss_end
; Stack init in main() (can override with avr-ld --defsym __stack=...)
! .weak __stack
! __stack = RAMEND
; These too can be set with the avr-ld --defsym name=value option
; (MCUCR must be set up correctly to enable external SRAM).
--- 36,44 ----
.extern __bss_end
; Stack init in main() (can override with avr-ld --defsym __stack=...)
! ; .weak __stack
! ;__stack = RAMEND
! .extern __stack
; These too can be set with the avr-ld --defsym name=value option
; (MCUCR must be set up correctly to enable external SRAM).
***************
*** 55,70 ****
; after reset, without any initialization at all. When done,
; it should jump to _real_init_.
.weak _U(_init_)
!
! .macro VEC name def
! .if . - .__start_of_init__ - \def
! .err
! .endif
! .weak _U(\name)
! #if !defined (__AVR_ASM_ONLY__)
! .set _U(\name), _unexpected_1_
! #endif
! XJMP _U(\name)
.endm
; reset and interrupt vectors, starting at absolute address 0
--- 56,74 ----
; after reset, without any initialization at all. When done,
; it should jump to _real_init_.
.weak _U(_init_)
! ;
! ; Vector table macros
! ;
! .set no_vect, 0
! .macro VEC name
! .if (END_VECTOR > no_vect)
! .weak _U(\name)
! #if !defined (__AVR_ASM_ONLY__)
! .set _U(\name), _unexpected_1_
! #endif
! XJMP _U(\name)
! .endif
! .set no_vect, no_vect + 1
.endm
; reset and interrupt vectors, starting at absolute address 0
***************
*** 73,216 ****
.func .__start_of_init__
.__start_of_init__:
XJMP _U(_init_)
! /* some devices have interrupt vectors in different order */
! #if defined (__AVR_AT94K__)
! /* many more interrupt vectors (some in different order) than other devices */
! VEC _fpga_int0_, FPGA_INT0_vect
! VEC _interrupt0_, INT0_vect
! VEC _fpga_int1_, FPGA_INT1_vect
! VEC _interrupt1_, INT1_vect
! VEC _fpga_int2_, FPGA_INT2_vect
! VEC _interrupt2_, INT2_vect
! VEC _fpga_int3_, FPGA_INT3_vect
! VEC _interrupt3_, INT3_vect
! VEC _output_compare2_, TIMER2_COMP_vect
! VEC _overflow2_, TIMER2_OVF_vect
! VEC _input_capture1_, TIMER1_CAPT_vect
! VEC _output_compare1a_, TIMER1_COMPA_vect
! VEC _output_compare1b_, TIMER1_COMPB_vect
! VEC _overflow1_, TIMER1_OVF_vect
! VEC _output_compare0_, TIMER0_COMP_vect
! VEC _overflow0_, TIMER0_OVF_vect
! VEC _fpga_int4_, FPGA_INT4_vect
! VEC _fpga_int5_, FPGA_INT5_vect
! VEC _fpga_int6_, FPGA_INT6_vect
! VEC _fpga_int7_, FPGA_INT7_vect
! VEC _uart_recv_, UART_RX_vect
! VEC _uart_data_, UART_UDRE_vect
! VEC _uart_trans_, UART_TX_vect
! VEC _fpga_int8_, FPGA_INT8_vect
! VEC _fpga_int9_, FPGA_INT9_vect
! VEC _fpga_int10_, FPGA_INT10_vect
! VEC _fpga_int11_, FPGA_INT11_vect
! VEC _uart1_recv_, UART1_RX_vect
! VEC _uart1_data_, UART1_UDRE_vect
! VEC _uart1_trans_, UART1_TX_vect
! VEC _fpga_int12_, FPGA_INT12_vect
! VEC _fpga_int13_, FPGA_INT13_vect
! VEC _fpga_int14_, FPGA_INT14_vect
! VEC _fpga_int15_, FPGA_INT15_vect
! VEC _twi_, TWI_INT_vect
! #elif defined (__AVR_ATtiny15__)
! VEC _interrupt0_, INT0_vect
! VEC _pin_change_, PIN_vect
! VEC _output_compare1a_, TIMER1_COMPA_vect
! VEC _overflow1_, TIMER1_OVF_vect
! VEC _overflow0_, TIMER0_OVF_vect
! VEC _eeprom_ready_, EE_RDY_vect
! VEC _comparator_, ANA_COMP_vect
! VEC _adc_, ADC_vect /* below _eeprom_ready_ in other devices */
! #else /* most other devices (not AT94K, not ATtiny15) */
! #ifdef INT0_vect
! VEC _interrupt0_, INT0_vect
! #endif
! #ifdef INT1_vect
! VEC _interrupt1_, INT1_vect
! #endif
! #ifdef INT2_vect
! VEC _interrupt2_, INT2_vect
! #endif
! #ifdef INT3_vect
! VEC _interrupt3_, INT3_vect
! #endif
! #ifdef INT4_vect
! VEC _interrupt4_, INT4_vect
! #endif
! #ifdef INT5_vect
! VEC _interrupt5_, INT5_vect
! #endif
! #ifdef INT6_vect
! VEC _interrupt6_, INT6_vect
! #endif
! #ifdef INT7_vect
! VEC _interrupt7_, INT7_vect
! #endif
! #ifdef PIN_vect
! VEC _pin_change_, PIN_vect
! #endif
! #ifdef TIMER2_COMP_vect
! VEC _output_compare2_, TIMER2_COMP_vect
! #endif
! #ifdef TIMER2_OVF_vect
! VEC _overflow2_, TIMER2_OVF_vect
! #endif
! #ifdef TIMER1_CAPT_vect
! VEC _input_capture1_, TIMER1_CAPT_vect
! #endif
! #ifdef TIMER1_COMPA_vect
! VEC _output_compare1a_, TIMER1_COMPA_vect
! #endif
! #ifdef TIMER1_COMPB_vect
! VEC _output_compare1b_, TIMER1_COMPB_vect
! #endif
! #ifdef TIMER1_OVF_vect
! VEC _overflow1_, TIMER1_OVF_vect
! #endif
! #ifdef TIMER0_COMP_vect
! VEC _output_compare0_, TIMER0_COMP_vect
! #endif
! #ifdef TIMER0_OVF_vect
! VEC _overflow0_, TIMER0_OVF_vect
! #endif
! #ifdef SPI_STC_vect
! VEC _spi_, SPI_STC_vect
! #endif
! #ifdef UART_RX_vect
! VEC _uart_recv_, UART_RX_vect
! #endif
! #ifdef UART1_RX_vect
! VEC _uart1_recv_, UART1_RX_vect
! #endif
! #ifdef UART_UDRE_vect
! VEC _uart_data_, UART_UDRE_vect
! #endif
! #ifdef UART1_UDRE_vect
! VEC _uart1_data_, UART1_UDRE_vect
! #endif
! #ifdef UART_TX_vect
! VEC _uart_trans_, UART_TX_vect
! #endif
! #ifdef UART1_TX_vect
! VEC _uart1_trans_, UART1_TX_vect
! #endif
! #ifdef ADC_vect
! VEC _adc_, ADC_vect
! #endif
! #ifdef EE_RDY_vect
! VEC _eeprom_ready_, EE_RDY_vect
! #endif
! #ifdef ANA_COMP_vect
! VEC _comparator_, ANA_COMP_vect
! #endif
! #ifdef TWI_INT_vect
! VEC _twi_, TWI_INT_vect
! #endif
! #endif /* most other devices (not AT94K, not ATtiny15) */
/* extra check */
! .if . - .__start_of_init__ - INT_VECT_SIZE
! .err
! .endif
.endfunc
--- 77,127 ----
.func .__start_of_init__
.__start_of_init__:
XJMP _U(_init_)
!
! VEC _vector_1
! VEC _vector_2
! VEC _vector_3
! VEC _vector_4
! VEC _vector_5
! VEC _vector_6
! VEC _vector_7
! VEC _vector_8
! VEC _vector_9
! VEC _vector_10
! VEC _vector_11
! VEC _vector_12
! VEC _vector_13
! VEC _vector_14
! VEC _vector_15
! VEC _vector_16
! VEC _vector_17
! VEC _vector_18
! VEC _vector_19
! VEC _vector_20
! VEC _vector_21
! VEC _vector_22
! VEC _vector_23
! VEC _vector_24
! VEC _vector_25
! VEC _vector_26
! VEC _vector_27
! VEC _vector_28
! VEC _vector_29
! VEC _vector_30
! VEC _vector_31
! VEC _vector_32
! VEC _vector_33
! VEC _vector_34
! VEC _vector_35
! VEC _vector_36
! VEC _vector_37
! VEC _vector_38
! VEC _vector_39
/* extra check */
! ; .if . - .__start_of_init__ - INT_VECT_SIZE
! ; .err
! ; .endif
.endfunc
***************
*** 222,244 ****
#define r_tmp1 r18
#define r_tmp2 r19
.global _U(_real_init_)
_U(_real_init_):
_U(_init_):
clr __zero_reg__
! out SREG, __zero_reg__
#ifdef WDTCR
ldi r_tmp1, lo8(__init_wdtcr__)
wdr
! out WDTCR, r_tmp1
#endif
#ifdef MCUCR
ldi r_tmp1, lo8(__init_mcucr__)
! out MCUCR, r_tmp1
#endif
#ifdef EMCUCR
ldi r_tmp1, lo8(__init_emcucr__)
! out EMCUCR, r_tmp1
#endif
; XXX should we also read, save and clear MCUSR (if present) here?
; (datasheets suggest to do it as soon as possible after reset)
--- 133,164 ----
#define r_tmp1 r18
#define r_tmp2 r19
+ /*
+ * I/O instructions below (out) require an address < 0x40.
+ * If an SFR offset is being used, the register address needs to be
+ * scaled back from its DATA memory address to its I/O memory address.
+ */
+ #ifndef __SFR_OFFSET
+ #define __SFR_OFFSET 0
+ #endif /* !__SFR_OFFSET */
+
.global _U(_real_init_)
_U(_real_init_):
_U(_init_):
clr __zero_reg__
! out (SREG - __SFR_OFFSET), __zero_reg__
#ifdef WDTCR
ldi r_tmp1, lo8(__init_wdtcr__)
wdr
! out (WDTCR - __SFR_OFFSET), r_tmp1
#endif
#ifdef MCUCR
ldi r_tmp1, lo8(__init_mcucr__)
! out (MCUCR - __SFR_OFFSET), r_tmp1
#endif
#ifdef EMCUCR
ldi r_tmp1, lo8(__init_emcucr__)
! out (EMCUCR - __SFR_OFFSET), r_tmp1
#endif
; XXX should we also read, save and clear MCUSR (if present) here?
; (datasheets suggest to do it as soon as possible after reset)
***************
*** 294,297 ****
.endfunc
#endif /* if !defined (__AVR_ASM_ONLY__) */
-
--- 214,216 ----
diff -rc3P avr-libc-20011029/src/macros.inc
avr-libc-20011029-patch-0.2/src/macros.inc
*** avr-libc-20011029/src/macros.inc Sun Oct 29 04:43:24 2000
--- avr-libc-20011029-patch-0.2/src/macros.inc Sun Nov 11 11:29:21 2001
***************
*** 17,22 ****
--- 17,26 ----
#include <io-avr.h>
+ #ifndef __SFR_OFFSET
+ #define __SFR_OFFSET 0
+ #endif
+
/* if not defined, assume old version with underscores */
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
***************
*** 161,167 ****
.macro LPM_R0_ZPLUS_INIT hhi
#if __AVR_ENHANCED__
#if BIG_CODE
! out RAMPZ, \hhi
#endif
#endif
.endm
--- 165,171 ----
.macro LPM_R0_ZPLUS_INIT hhi
#if __AVR_ENHANCED__
#if BIG_CODE
! out (RAMPZ-__SFR_OFFSET), \hhi
#endif
#endif
.endm
***************
*** 178,184 ****
#else
#if BIG_CODE
/* ELPM without post-increment, load RAMPZ each time (ATmega103) */
! out RAMPZ, \hhi
elpm
adiw ZL, 1
adc \hhi, __zero_reg__
--- 182,188 ----
#else
#if BIG_CODE
/* ELPM without post-increment, load RAMPZ each time (ATmega103) */
! out (RAMPZ-__SFR_OFFSET), \hhi
elpm
adiw ZL, 1
adc \hhi, __zero_reg__
diff -rc3P binutils-2.11.2/gas/config/tc-avr.c
binutils-2.11.2-patch-0.1/gas/config/tc-avr.c
*** binutils-2.11.2/gas/config/tc-avr.c Thu Jun 7 13:15:28 2001
--- binutils-2.11.2-patch-0.1/gas/config/tc-avr.c Tue Nov 6 18:58:48 2001
***************
*** 87,92 ****
--- 87,93 ----
{"atmega163", AVR_ISA_M161, bfd_mach_avr5},
{"atmega32", AVR_ISA_M161, bfd_mach_avr5},
{"at94k", AVR_ISA_94K, bfd_mach_avr5},
+ {"atmega128", AVR_ISA_M128, bfd_mach_avr5},
{NULL, 0, 0}
};
***************
*** 258,264 ****
" avr2 - AT90S2xxx, AT90S4xxx, AT90S8xxx, ATtiny22\n"
" avr3 - ATmega103, ATmega603\n"
" avr4 - ATmega83, ATmega85\n"
! " avr5 - ATmega161, ATmega163, ATmega32, AT94K\n"
" or immediate microcontroller name.\n"));
fprintf (stream,
_(" -mall-opcodes accept all AVR opcodes, even if not supported by
MCU\n"
--- 259,265 ----
" avr2 - AT90S2xxx, AT90S4xxx, AT90S8xxx, ATtiny22\n"
" avr3 - ATmega103, ATmega603\n"
" avr4 - ATmega83, ATmega85\n"
! " avr5 - ATmega161, ATmega163, ATmega32, AT94K,
ATmega128\n"
" or immediate microcontroller name.\n"));
fprintf (stream,
_(" -mall-opcodes accept all AVR opcodes, even if not supported by
MCU\n"
diff -rc3P binutils-2.11.2/include/opcode/avr.h
binutils-2.11.2-patch-0.1/include/opcode/avr.h
*** binutils-2.11.2/include/opcode/avr.h Mon Aug 7 00:09:14 2000
--- binutils-2.11.2-patch-0.1/include/opcode/avr.h Wed Nov 7 12:26:47 2001
***************
*** 34,39 ****
--- 34,40 ----
#define AVR_ISA_M83 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
+ #define AVR_ISA_M128 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX |
AVR_ISA_ELPMX )
#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX)
diff -rc3P binutils-2.11.2/ld/Makefile.am
binutils-2.11.2-patch-0.1/ld/Makefile.am
*** binutils-2.11.2/ld/Makefile.am Mon Jun 11 20:05:07 2001
--- binutils-2.11.2-patch-0.1/ld/Makefile.am Wed Nov 7 13:43:15 2001
***************
*** 119,124 ****
--- 119,125 ----
eavr44x4.o \
eavr85xx.o \
eavrmega103.o \
+ eavrmega128.o \
eavrmega161.o \
eavrmega603.o \
ecoff_sparc.o \
***************
*** 380,385 ****
--- 381,390 ----
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elf32avr.sc \
${GEN_DEPENDS}
${GENSCRIPTS} avrmega103 "$(tdir_avr85xx)"
+ eavrmega128.c: $(srcdir)/emulparams/avrmega128.sh \
+ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elf32avr.sc \
+ ${GEN_DEPENDS}
+ ${GENSCRIPTS} avrmega128 "$(tdir_avr85xx)"
eavrmega161.c: $(srcdir)/emulparams/avrmega161.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elf32avr.sc \
${GEN_DEPENDS}
diff -rc3P binutils-2.11.2/ld/Makefile.in
binutils-2.11.2-patch-0.1/ld/Makefile.in
*** binutils-2.11.2/ld/Makefile.in Mon Jun 11 20:05:07 2001
--- binutils-2.11.2-patch-0.1/ld/Makefile.in Wed Nov 7 13:43:48 2001
***************
*** 227,232 ****
--- 227,233 ----
eavr44x4.o \
eavr85xx.o \
eavrmega103.o \
+ eavrmega128.o \
eavrmega161.o \
eavrmega603.o \
ecoff_sparc.o \
***************
*** 1094,1099 ****
--- 1095,1104 ----
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elf32avr.sc \
${GEN_DEPENDS}
${GENSCRIPTS} avrmega103 "$(tdir_avr85xx)"
+ eavrmega128.c: $(srcdir)/emulparams/avrmega128.sh \
+ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elf32avr.sc \
+ ${GEN_DEPENDS}
+ ${GENSCRIPTS} avrmega128 "$(tdir_avr85xx)"
eavrmega161.c: $(srcdir)/emulparams/avrmega161.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elf32avr.sc \
${GEN_DEPENDS}
diff -rc3P binutils-2.11.2/ld/configure.tgt
binutils-2.11.2-patch-0.1/ld/configure.tgt
*** binutils-2.11.2/ld/configure.tgt Mon Jun 11 20:05:08 2001
--- binutils-2.11.2-patch-0.1/ld/configure.tgt Wed Nov 7 13:44:17 2001
***************
*** 22,28 ****
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
arc-*-elf*) targ_emul=arcelf ;;
avr-*-*) targ_emul=avr85xx
! targ_extra_emuls="avr1200 avr23xx avr44x4 avr4433
avrmega603 avrmega103 avrmega161" ;;
cris-*-*aout*) targ_emul=crisaout
targ_extra_emuls="criself crislinux"
targ_extra_libpath=$targ_extra_emuls ;;
--- 22,28 ----
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
arc-*-elf*) targ_emul=arcelf ;;
avr-*-*) targ_emul=avr85xx
! targ_extra_emuls="avr1200 avr23xx avr44x4 avr4433
avrmega603 avrmega103 avrmega128 avrmega161" ;;
cris-*-*aout*) targ_emul=crisaout
targ_extra_emuls="criself crislinux"
targ_extra_libpath=$targ_extra_emuls ;;
diff -rc3P binutils-2.11.2/ld/emulparams/avr1200.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avr1200.sh
*** binutils-2.11.2/ld/emulparams/avr1200.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avr1200.sh Sun Nov 11 08:57:42 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=1K
+ DATA_START=0x60
DATA_LENGTH=0
EEPROM_LENGTH=64
STACK=0
diff -rc3P binutils-2.11.2/ld/emulparams/avr23xx.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avr23xx.sh
*** binutils-2.11.2/ld/emulparams/avr23xx.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avr23xx.sh Sun Nov 11 08:57:51 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=2K
+ DATA_START=0x60
DATA_LENGTH=128
EEPROM_LENGTH=128
STACK=0x0DF
diff -rc3P binutils-2.11.2/ld/emulparams/avr4433.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avr4433.sh
*** binutils-2.11.2/ld/emulparams/avr4433.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avr4433.sh Sun Nov 11 08:58:00 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=4K
+ DATA_START=0x60
DATA_LENGTH=128
EEPROM_LENGTH=256
STACK=0x0DF
diff -rc3P binutils-2.11.2/ld/emulparams/avr44x4.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avr44x4.sh
*** binutils-2.11.2/ld/emulparams/avr44x4.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avr44x4.sh Sun Nov 11 08:58:10 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=4K
+ DATA_START=0x60
DATA_LENGTH=256
EEPROM_LENGTH=256
STACK=0x15F
diff -rc3P binutils-2.11.2/ld/emulparams/avr85xx.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avr85xx.sh
*** binutils-2.11.2/ld/emulparams/avr85xx.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avr85xx.sh Sun Nov 11 08:58:16 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=8K
+ DATA_START=0x60
DATA_LENGTH=512
EEPROM_LENGTH=512
STACK=0x25F
diff -rc3P binutils-2.11.2/ld/emulparams/avrmega103.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avrmega103.sh
*** binutils-2.11.2/ld/emulparams/avrmega103.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avrmega103.sh Sun Nov 11
08:58:24 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=128K
+ DATA_START=0x60
DATA_LENGTH=4000
EEPROM_LENGTH=4K
STACK=0x0FFF
diff -rc3P binutils-2.11.2/ld/emulparams/avrmega128.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avrmega128.sh
*** binutils-2.11.2/ld/emulparams/avrmega128.sh Thu Jan 1 10:00:00 1970
--- binutils-2.11.2-patch-0.1/ld/emulparams/avrmega128.sh Sun Nov 11
09:00:44 2001
***************
*** 0 ****
--- 1,13 ----
+ ARCH=avr:5
+ MACHINE=
+ SCRIPT_NAME=elf32avr
+ OUTPUT_FORMAT="elf32-avr"
+ MAXPAGESIZE=1
+ EMBEDDED=yes
+ TEMPLATE_NAME=generic
+
+ TEXT_LENGTH=128K
+ DATA_START=0x100
+ DATA_LENGTH=4096
+ EEPROM_LENGTH=4K
+ STACK=0x10FF
diff -rc3P binutils-2.11.2/ld/emulparams/avrmega161.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avrmega161.sh
*** binutils-2.11.2/ld/emulparams/avrmega161.sh Tue Jun 27 11:45:30 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avrmega161.sh Sun Nov 11
09:00:50 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=16K
+ DATA_START=0x60
DATA_LENGTH=1K
EEPROM_LENGTH=512
STACK=0x45F
diff -rc3P binutils-2.11.2/ld/emulparams/avrmega603.sh
binutils-2.11.2-patch-0.1/ld/emulparams/avrmega603.sh
*** binutils-2.11.2/ld/emulparams/avrmega603.sh Sun May 28 01:36:58 2000
--- binutils-2.11.2-patch-0.1/ld/emulparams/avrmega603.sh Sun Nov 11
09:01:01 2001
***************
*** 7,12 ****
--- 7,13 ----
TEMPLATE_NAME=generic
TEXT_LENGTH=64K
+ DATA_START=0x60
DATA_LENGTH=4000
EEPROM_LENGTH=2K
STACK=0x0FFF
diff -rc3P binutils-2.11.2/ld/scripttempl/elf32avr.sc
binutils-2.11.2-patch-0.1/ld/scripttempl/elf32avr.sc
*** binutils-2.11.2/ld/scripttempl/elf32avr.sc Tue Nov 14 09:26:38 2000
--- binutils-2.11.2-patch-0.1/ld/scripttempl/elf32avr.sc Sun Nov 11
09:55:07 2001
***************
*** 5,11 ****
MEMORY
{
text (rx) : ORIGIN = 0, LENGTH = $TEXT_LENGTH
! data (rw!x) : ORIGIN = 0x800060, LENGTH = $DATA_LENGTH
eeprom (rw!x) : ORIGIN = 0x810000, LENGTH = $EEPROM_LENGTH
}
--- 5,11 ----
MEMORY
{
text (rx) : ORIGIN = 0, LENGTH = $TEXT_LENGTH
! data (rw!x) : ORIGIN = (0x800000 + $DATA_START), LENGTH = $DATA_LENGTH
eeprom (rw!x) : ORIGIN = 0x810000, LENGTH = $EEPROM_LENGTH
}
***************
*** 101,106 ****
--- 101,107 ----
*(.bss)
*(COMMON)
${RELOCATING+ PROVIDE (__bss_end = .) ; }
+ ${RELOCATING+ PROVIDE (end = .);}
${RELOCATING+ _end = . ; }
} ${RELOCATING+ > data}
diff -rc3P gcc-3.0.2/gcc/ChangeLog gcc-3.0.2-patch-0.1/gcc/ChangeLog
*** gcc-3.0.2/gcc/ChangeLog Wed Oct 24 03:19:18 2001
--- gcc-3.0.2-patch-0.1/gcc/ChangeLog Wed Nov 7 14:57:55 2001
***************
*** 1,3 ****
--- 1,9 ----
+ 2001-11-07 Peter Jansen <address@hidden>
+
+ * gcc/config/avr/avr.c - added mega128 to list of avr5 types
+ * gcc/config/avr/avr/h - Ditto
+
+
2001-10-23 Release Manager
* GCC 3.0.2 Released.
diff -rc3P gcc-3.0.2/gcc/config/avr/avr.c
gcc-3.0.2-patch-0.1/gcc/config/avr/avr.c
*** gcc-3.0.2/gcc/config/avr/avr.c Thu Jun 28 07:35:37 2001
--- gcc-3.0.2-patch-0.1/gcc/config/avr/avr.c Tue Nov 6 18:35:24 2001
***************
*** 153,158 ****
--- 153,159 ----
{ "atmega163", AVR5 },
{ "atmega32", AVR5 },
{ "at94k", AVR5 },
+ { "atmega128", AVR5 },
/* Assembler only. */
{ "avr1", AVR1 },
{ "at90s1200", AVR1 },
***************
*** 1164,1170 ****
/* Choose mode for jump insn:
1 - relative jump in range -63 <= x <= 62 ;
2 - relative jump in range -2046 <= x <= 2045 ;
! 3 - absolute jump (only for ATmega[16]03). */
int
avr_jump_mode (x, insn)
--- 1165,1171 ----
/* Choose mode for jump insn:
1 - relative jump in range -63 <= x <= 62 ;
2 - relative jump in range -2046 <= x <= 2045 ;
! 3 - absolute jump (only for ATmega1[6][03][28]). */
int
avr_jump_mode (x, insn)
diff -rc3P gcc-3.0.2/gcc/config/avr/avr.h
gcc-3.0.2-patch-0.1/gcc/config/avr/avr.h
*** gcc-3.0.2/gcc/config/avr/avr.h Tue Apr 17 04:25:42 2001
--- gcc-3.0.2-patch-0.1/gcc/config/avr/avr.h Tue Nov 6 17:59:26 2001
***************
*** 2973,2978 ****
--- 2973,2979 ----
%{mmcu=avr3:%(cpp_avr3)} \
%{mmcu=atmega603:%(cpp_avr3) -D__AVR_ATmega603__} \
%{mmcu=atmega103:%(cpp_avr3) -D__AVR_ATmega103__} \
+ %{mmcu=atmega128:%(cpp_avr5) -D__AVR_ATmega128__} \
%{mmcu=avr4:%(cpp_avr4)} \
%{mmcu=atmega83: %(cpp_avr4) -D__AVR_ATmega83__} \
%{mmcu=atmega85: %(cpp_avr4) -D__AVR_ATmega85__} \
***************
*** 3051,3056 ****
--- 3052,3058 ----
%{!mmcu*:-m avr85xx} \
%{mmcu=atmega603:-m avrmega603} \
%{mmcu=atmega103:-m avrmega103} \
+ %{mmcu=atmega128:-m avrmega128} \
%{mmcu=atmega161:-m avrmega161} \
%{mmcu=atmega163:-m avrmega161} \
%{mmcu=atmega32:-m avr5} \
***************
*** 3130,3135 ****
--- 3132,3138 ----
%{mmcu=at90c8534:crtc8534.o%s} \
%{mmcu=at90s8535:crts8535.o%s} \
%{mmcu=atmega103|mmcu=avr3:crtm103.o%s} \
+ %{mmcu=atmega128|mmcu=avr5:crtm128.o%s} \
%{mmcu=atmega603:crtm603.o%s} \
%{mmcu=atmega83|mmcu=avr4:crtm83.o%s} \
%{mmcu=atmega85:crtm85.o%s} \
diff -rc3P gcc-3.0.2/gcc/config/avr/t-avr
gcc-3.0.2-patch-0.1/gcc/config/avr/t-avr
*** gcc-3.0.2/gcc/config/avr/t-avr Sun Jan 21 03:49:01 2001
--- gcc-3.0.2-patch-0.1/gcc/config/avr/t-avr Tue Nov 6 18:02:33 2001
***************
*** 49,55 ****
mmcu?avr3=mmcu?atmega103 mmcu?avr3=mmcu?atmega603 \
mmcu?avr4=mmcu?atmega83 mmcu?avr4=mmcu?atmega85 \
mmcu?avr5=mmcu?atmega161 mmcu?avr5=mmcu?atmega163 \
! mmcu?avr5=mmcu?atmega32 mmcu?avr5=mmcu?at94k
MULTILIB_EXCEPTIONS =
--- 49,56 ----
mmcu?avr3=mmcu?atmega103 mmcu?avr3=mmcu?atmega603 \
mmcu?avr4=mmcu?atmega83 mmcu?avr4=mmcu?atmega85 \
mmcu?avr5=mmcu?atmega161 mmcu?avr5=mmcu?atmega163 \
! mmcu?avr5=mmcu?atmega32 mmcu?avr5=mmcu?at94k \
! mmcu?avr5=mmcu?atmega128
MULTILIB_EXCEPTIONS =