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[qemu-s390x] [PULL 08/15] s390x/tcg: store in the TB flags if AFP is ena
From: |
Cornelia Huck |
Subject: |
[qemu-s390x] [PULL 08/15] s390x/tcg: store in the TB flags if AFP is enabled |
Date: |
Thu, 4 Oct 2018 17:28:50 +0200 |
From: David Hildenbrand <address@hidden>
We exit the TB when changing the control registers, so just like PSW
bits, this should always be consistent for a TB.
Using the PSW bit semantic makes things a lot easier compared to
manually defining the spare, shifted bits.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
---
target/s390x/cpu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5e50c3a303..8c2320e882 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -255,6 +255,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
/* PSW defines */
#undef PSW_MASK_PER
+#undef PSW_MASK_UNUSED_2
#undef PSW_MASK_DAT
#undef PSW_MASK_IO
#undef PSW_MASK_EXT
@@ -273,6 +274,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#undef PSW_MASK_ESA_ADDR
#define PSW_MASK_PER 0x4000000000000000ULL
+#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
#define PSW_MASK_DAT 0x0400000000000000ULL
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
@@ -318,6 +320,9 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT |
FLAG_MASK_PSTATE \
| FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
+/* we'll use some unused PSW positions to store CR flags in tb flags */
+#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
+
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
#define CR0_SECONDARY 0x0000000004000000ULL
@@ -364,6 +369,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env,
target_ulong *pc,
*pc = env->psw.addr;
*cs_base = env->ex_value;
*flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ if (env->cregs[0] & CR0_AFP) {
+ *flags |= FLAG_MASK_AFP;
+ }
}
/* PER bits from control register 9 */
--
2.14.4
- [qemu-s390x] [PULL 00/15] s390x updates, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 01/15] hw/s390x/ipl: Fix alignment problems of S390IPLState members, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 04/15] s390x: Fence huge pages prior to 3.1, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 05/15] target/s390x: exception on non-aligned LPSW(E), Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 02/15] hw/s390x/css: Remove QEMU_PACKED from struct SenseId, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 06/15] s390x: move tcg_s390_program_interrupt() into TCG code and mark it noreturn, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 07/15] s390x/tcg: factor out and fix DATA exception injection, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 08/15] s390x/tcg: store in the TB flags if AFP is enabled,
Cornelia Huck <=
- [qemu-s390x] [PULL 09/15] s390x/tcg: support flags for instructions, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 10/15] s390x/tcg: add instruction flags for floating point instructions, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 11/15] s390x/tcg: check for AFP-register, BFP and DFP data exceptions, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 14/15] s390x/tcg: refactor specification checking, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 12/15] s390x/tcg: handle privileged instructions via flags, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 13/15] s390x/tcg: fix FP register pair checks, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 15/15] hw/s390x/s390-pci-bus: Convert sysbus init function to realize function, Cornelia Huck, 2018/10/04
- [qemu-s390x] [PULL 03/15] hw/s390x/ioinst: Fix alignment problem in struct SubchDev, Cornelia Huck, 2018/10/04
- Re: [qemu-s390x] [PULL 00/15] s390x updates, Peter Maydell, 2018/10/05