Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

[Deepak Gupta]

On Fri, Jan 05, 2024 at 10:33:40AM +0300, Alexey Baturo wrote:
> I think you're right, thanks.
> I'll add a check for M-mode as well and I guess I'll have to rename the
> function.
> Any ideas on the proper and self-describing name?

Since all we care for is whether virtual memory is enabled and in effect or not.
Some suggestions below
`
bool riscv_cpu_mmu_enabled
bool riscv_cpu_paging_enabled
bool riscv_cpu_virt_mem_enabled


> Thanks
>
> пт, 5 янв. 2024 г. в 03:46, Deepak Gupta <debug@rivosinc.com>:
>
> > On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com>
> > wrote:
> > > +
> > > +bool riscv_cpu_bare_mode(CPURISCVState *env)
> > > +{
> > > +    int satp_mode = 0;
> > > +#ifndef CONFIG_USER_ONLY
> > > +    if (riscv_cpu_mxl(env) == MXL_RV32) {
> > > +        satp_mode = get_field(env->satp, SATP32_MODE);
> > > +    } else {
> > > +        satp_mode = get_field(env->satp, SATP64_MODE);
> > > +    }
> > > +#endif
> > > +    return (satp_mode == VM_1_10_MBARE);
> > > +}
> > > +
> >
> > Assume the CPU was in S or U with satp = non-bare mode but then a
> > transfer to M-mode happened.
> > In that case, even though the CPU is in M mode, the above function
> > will return non-bare mode and enforce
> > signed extension on M mode pointer masking (if enabled).
> >
> > right or am I missing something here?