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[PATCH v2 2/6] target/riscv: Don't assume PMU counters are continuous
From: |
Rob Bradford |
Subject: |
[PATCH v2 2/6] target/riscv: Don't assume PMU counters are continuous |
Date: |
Wed, 11 Oct 2023 15:45:50 +0100 |
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 85a31dc420..3e126219ba 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -182,7 +182,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
- int pmu_num = riscv_cpu_cfg(env)->pmu_num;
+ RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs;
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@@ -191,7 +192,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
- if (!pmu_num || ctr_index >= pmu_num) {
+ if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) {
/* The PMU is not enabled or counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.41.0