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[PATCH v5 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v5 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() |
Date: |
Tue, 28 Mar 2023 14:35:40 -0300 |
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 50 ++++++++++++++++++++++++++++++----------------
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a9042b190d..05878846f9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -867,6 +867,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU
*cpu)
}
}
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ CPUClass *cc = CPU_CLASS(mcc);
+ CPURISCVState *env = &cpu->env;
+
+ /* Validate that MISA_MXL is set properly. */
+ switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ case MXL_RV128:
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+ break;
+#endif
+ case MXL_RV32:
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (env->misa_mxl_max != env->misa_mxl) {
+ error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
+ return;
+ }
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -1135,7 +1162,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
- CPUClass *cc = CPU_CLASS(mcc);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -1144,6 +1170,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ riscv_cpu_validate_misa_mxl(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
riscv_cpu_validate_priv_spec(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -1172,22 +1204,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
#endif /* CONFIG_USER_ONLY */
- /* Validate that MISA_MXL is set properly. */
- switch (env->misa_mxl_max) {
-#ifdef TARGET_RISCV64
- case MXL_RV64:
- case MXL_RV128:
- cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
- break;
-#endif
- case MXL_RV32:
- cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
- default:
- g_assert_not_reached();
- }
- assert(env->misa_mxl_max == env->misa_mxl);
-
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.39.2
- [PATCH v5 0/9] target/riscv: rework CPU extensions validation, Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v(), Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 2/9] target/riscv/cpu.c: remove set_vext_version(), Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 3/9] target/riscv/cpu.c: remove set_priv_version(), Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 4/9] target/riscv: add PRIV_VERSION_LATEST, Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(),
Daniel Henrique Barboza <=
- [PATCH v5 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init(), Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Daniel Henrique Barboza, 2023/03/28
- [PATCH v5 9/9] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/28