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[PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage
From: |
Richard Henderson |
Subject: |
[PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage |
Date: |
Sat, 25 Mar 2023 03:54:18 -0700 |
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 1 -
target/riscv/internals.h | 5 +++++
target/riscv/cpu_helper.c | 17 ++++++-----------
3 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f03ff1f10c..b6bcfb3834 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -586,7 +586,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong
geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int
mmu_idx,
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 4aa1cb409f..b5f823c7ec 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -51,6 +51,11 @@ static inline bool mmuidx_sum(int mmu_idx)
return (mmu_idx & 3) == MMUIdx_S_SUM;
}
+static inline bool mmuidx_2stage(int mmu_idx)
+{
+ return mmu_idx & MMU_2STAGE_BIT;
+}
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index cb260b88ea..8a124888cd 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -603,11 +603,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
}
}
-bool riscv_cpu_two_stage_lookup(int mmu_idx)
-{
- return mmu_idx & MMU_2STAGE_BIT;
-}
-
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
{
CPURISCVState *env = &cpu->env;
@@ -791,7 +786,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
/* MPRV does not affect the virtual-machine load/store
instructions, HLV, HLVX, and HSV. */
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
}
@@ -1177,7 +1172,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
env->badaddr = addr;
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1203,7 +1198,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
}
env->badaddr = addr;
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1255,7 +1250,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
/* MPRV does not affect the virtual-machine load/store
instructions, HLV, HLVX, and HSV. */
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
@@ -1267,7 +1262,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
pmu_tlb_fill_incr_ctr(cpu, access_type);
if (riscv_cpu_virt_enabled(env) ||
- ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
+ ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
@@ -1365,7 +1360,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error,
riscv_cpu_virt_enabled(env) ||
- riscv_cpu_two_stage_lookup(mmu_idx),
+ mmuidx_2stage(mmu_idx),
two_stage_indirect_error);
cpu_loop_exit_restore(cs, retaddr);
}
--
2.34.1
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, (continued)
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/03/25
- [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/03/25
- [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop, Richard Henderson, 2023/03/25
- [PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Richard Henderson, 2023/03/25
- [PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/03/25
- [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv, Richard Henderson, 2023/03/25
- [PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage,
Richard Henderson <=
- [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/03/25
- [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags, Richard Henderson, 2023/03/25
- [PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX, Richard Henderson, 2023/03/25
- [PATCH v6 02/25] target/riscv: Add a general status enum for extensions, Richard Henderson, 2023/03/25
- [PATCH v6 08/25] accel/tcg: Add cpu_ld*_code_mmu, Richard Henderson, 2023/03/25
- [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Richard Henderson, 2023/03/25