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[PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa(
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa() |
Date: |
Wed, 22 Mar 2023 19:20:04 -0300 |
RVG is enabled when IMAFD_Zicsr_Zifencei is also enabled. Change
write_misa() to enable IMAFD if G is being written in the CSR.
Likewise, RVG should be disabled if any of IMAFD got disabled during the
process. Clear RVG in this case.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/csr.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 839862f1a8..1c0f438dfb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1381,6 +1381,14 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
val &= RVE;
}
+ if (val & RVG && !(env->misa_ext & RVG)) {
+ /*
+ * If the write wants to enable RVG, enable all its
+ * dependencies as well.
+ */
+ val |= RVI | RVM | RVA | RVF | RVD;
+ }
+
/*
* This flow is similar to what riscv_cpu_realize() does,
* with the difference that we will update env->misa_ext
@@ -1396,6 +1404,12 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+ if (!(val & RVI && val & RVM && val & RVA &&
+ val & RVF && val & RVD)) {
+ /* Disable RVG if any of its dependencies were disabled */
+ val &= ~RVG;
+ }
+
riscv_cpu_commit_cpu_cfg(cpu, val);
if (!(val & RVF)) {
--
2.39.2
- [PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions validation, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 06/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 13/25] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 v4 23/25] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 05/25] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 01/25] target/riscv/cpu.c: add riscv_cpu_validate_v(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 16/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 02/25] target/riscv/cpu.c: remove set_vext_version(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 03/25] target/riscv/cpu.c: remove set_priv_version(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 04/25] target/riscv: add PRIV_VERSION_LATEST, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 12/25] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/22