[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa()
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa() |
Date: |
Wed, 8 Mar 2023 17:19:24 -0300 |
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation step in
riscv_cpu_validate_set_extensions(). This means that enabling G will
enable other extensions in the CPU before resuming the validation.
This also means that, in case a write_misa() validation fails, we're
going to set cpu->cfg attributes that are unrelated to misa_ext bits
(icsr and ifencei). These would be 2 extra states that we would need to
store to fallback from a validation failure.
Since write_misa() is still on experimental state let's make our lives
easier for now and disable RVG updates.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ab566639e5..02a5c2a5ca 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1347,6 +1347,11 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+ /* Changing 'G' state is unsupported */
+ if (val & RVG) {
+ return RISCV_EXCP_NONE;
+ }
+
/* 'I' or 'E' must be present */
if (!(val & (RVI | RVE))) {
/* It is not, drop write to misa */
--
2.39.2
- [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), (continued)
- [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 15/17] target/riscv: add RVG, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 17/17] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/08
- Re: [PATCH for-8.1 00/17] centralize CPU extensions logic, Daniel Henrique Barboza, 2023/03/09