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[PATCH v2 12/14] target/riscv: Fix check for vector load/store instructi
From: |
Weiwei Li |
Subject: |
[PATCH v2 12/14] target/riscv: Fix check for vector load/store instructions when EEW=64 |
Date: |
Wed, 15 Feb 2023 10:05:37 +0800 |
The V extension supports all vector load and store instructions except
the V extension does not support EEW=64 for index values when XLEN=32.
(Section 18.3)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9b2c5c9ac0..5dbdce073b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -287,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd,
int vs2, int nf,
require_nf(vd, nf, s->lmul);
/*
- * All Zve* extensions support all vector load and store instructions,
- * except Zve64* extensions do not support EEW=64 for index values
- * when XLEN=32. (Section 18.2)
+ * V extension supports all vector load and store instructions,
+ * except V extension does not support EEW=64 for index values
+ * when XLEN=32. (Section 18.3)
*/
if (get_xl(s) == MXL_RV32) {
- ret &= (!has_ext(s, RVV) &&
- s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
+ ret &= (eew != MO_64);
}
return ret;
--
2.25.1
- Re: [PATCH v2 05/14] target/riscv: Fix relationship between V, Zve*, F and D, (continued)
- [PATCH v2 04/14] target/riscv: Add cfg properties for Zv* extensions, Weiwei Li, 2023/02/14
- [PATCH v2 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
- [PATCH v2 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Weiwei Li, 2023/02/14
- [PATCH v2 14/14] target/riscv: Expose properties for Zv* extensions, Weiwei Li, 2023/02/14
- [PATCH v2 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Weiwei Li, 2023/02/14
- [PATCH v2 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
- [PATCH v2 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
- [PATCH v2 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Weiwei Li, 2023/02/14
- [PATCH v2 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14
- [PATCH v2 12/14] target/riscv: Fix check for vector load/store instructions when EEW=64,
Weiwei Li <=
- [PATCH v2 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Weiwei Li, 2023/02/14