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[Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f
From: |
Weiwei Li |
Subject: |
[Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f |
Date: |
Tue, 14 Feb 2023 16:38:27 +0800 |
Zve64f depends on Zve32f, so we can only check Zve32f
in these cases
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index bbb5c3a7b5..6f7ecf1a68 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,
TCGv s2)
{
TCGv s1, dst;
- if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
- s->cfg_ptr->ext_zve64f)) {
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
return false;
}
@@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1,
TCGv s2)
{
TCGv dst;
- if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
- s->cfg_ptr->ext_zve64f)) {
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
return false;
}
--
2.25.1
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, (continued)
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Weiwei Li, 2023/02/14
- [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
- [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
- [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Weiwei Li, 2023/02/14
- [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f,
Weiwei Li <=
- [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
- [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Weiwei Li, 2023/02/14
- [Patch 14/14] target/riscv: Expose properties for Zv* extension, Weiwei Li, 2023/02/14
- [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14