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[PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken
From: |
Anup Patel |
Subject: |
[PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode |
Date: |
Wed, 11 May 2022 20:15:22 +0530 |
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1aa4f2097..b16bfe0182 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1367,7 +1367,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
case RISCV_EXCP_INST_PAGE_FAULT:
case RISCV_EXCP_LOAD_PAGE_FAULT:
case RISCV_EXCP_STORE_PAGE_FAULT:
- write_gva = true;
+ write_gva = env->two_stage_lookup;
tval = env->badaddr;
break;
case RISCV_EXCP_ILLEGAL_INST:
@@ -1434,7 +1434,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
/* Trap into HS mode */
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
htval = env->guest_phys_fault_addr;
- write_gva = false;
}
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
}
--
2.34.1
- [PATCH v2 0/8] QEMU RISC-V nested virtualization fixes, Anup Patel, 2022/05/11
- [PATCH v2 1/8] target/riscv: Fix csr number based privilege checking, Anup Patel, 2022/05/11
- [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode,
Anup Patel <=
- [PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Anup Patel, 2022/05/11
- [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Anup Patel, 2022/05/11
- [PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest, Anup Patel, 2022/05/11
- [PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher, Anup Patel, 2022/05/11
- [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match, Anup Patel, 2022/05/11