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[PATCH 0/2] target/riscv: Annotate atomic operations
From: |
Richard Henderson |
Subject: |
[PATCH 0/2] target/riscv: Annotate atomic operations |
Date: |
Fri, 1 Apr 2022 06:59:46 -0600 |
If an atomic operation fails on RISC-V, we want to generate
a store/amo fault and not a load fault.
Annotate amo insns, so that we can recognize them after unwinding.
Transform the implementation access type to store/amo for reporting.
r~
Richard Henderson (2):
target/riscv: Use cpu_loop_exit_restore directly from mmu faults
target/riscv: Mark amo insns during translation
target/riscv/cpu.h | 15 ++++++
target/riscv/cpu.c | 3 ++
target/riscv/cpu_helper.c | 62 +++++++++++++++++--------
target/riscv/translate.c | 9 ++++
target/riscv/insn_trans/trans_rva.c.inc | 11 ++++-
5 files changed, 79 insertions(+), 21 deletions(-)
--
2.25.1
- [PATCH 0/2] target/riscv: Annotate atomic operations,
Richard Henderson <=