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Re: [PATCH v4 0/3] RISC-V: Populate mtval and stval
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 0/3] RISC-V: Populate mtval and stval |
Date: |
Fri, 7 Jan 2022 13:33:19 +1000 |
On Mon, Dec 20, 2021 at 4:49 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Populate mtval and stval when taking an illegal instruction exception.
>
> The RISC-V spec states that "The stval register can optionally also be
> used to return the faulting instruction bits on an illegal instruction
> exception...". In this case we are always writing the value on an
> illegal instruction.
>
> This doesn't match all CPUs (some CPUs won't write the data), but in
> QEMU let's just populate the value on illegal instructions. This won't
> break any guest software, but will provide more information to guests.
>
> Alistair Francis (3):
> target/riscv: Set the opcode in DisasContext
> target/riscv: Fixup setting GVA
> target/riscv: Implement the stval/mtval illegal instruction
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_helper.c | 24 +++++++++---------------
> target/riscv/translate.c | 5 +++++
> 3 files changed, 16 insertions(+), 15 deletions(-)
>
> --
> 2.31.1
>
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