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[PATCH 2/6] target/riscv: add support for unique fpr read/write with sup
From: |
liweiwei |
Subject: |
[PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx |
Date: |
Fri, 24 Dec 2021 11:49:11 +0800 |
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
---
target/riscv/translate.c | 169 +++++++++++++++++++++++++++++++++++++++
1 file changed, 169 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8b1cdacf50..bac42e60bd 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -104,10 +104,13 @@ typedef struct DisasContext {
target_ulong vstart;
bool vl_eq_vlmax;
uint8_t ntemp;
+ uint8_t nftemp;
CPUState *cs;
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
+ /* Space for 4 float point operands */
+ TCGv_i64 ftemp[4];
/* PointerMasking extension */
bool pm_enabled;
TCGv pm_mask;
@@ -295,6 +298,165 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num,
TCGv t)
}
}
+static TCGv_i64 ftemp_new(DisasContext *ctx)
+{
+ assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp));
+ return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64();
+}
+
+static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
+{
+ if (ctx->ext_zfinx) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+#ifdef TARGET_RISCV32
+ {
+ TCGv_i64 t = ftemp_new(ctx);
+ if (reg_num == 0) {
+ tcg_gen_concat_i32_i64(t, ctx->zero, ctx->zero);
+ } else {
+ tcg_gen_concat_i32_i64(t, cpu_gpr[reg_num], ctx->zero);
+ }
+ return t;
+ }
+#else
+ /* fall through */
+ case MXL_RV64:
+ if (reg_num == 0) {
+ return ctx->zero;
+ } else {
+ return cpu_gpr[reg_num];
+ }
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ return cpu_fpr[reg_num];
+ }
+}
+
+static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
+{
+ if (ctx->ext_zfinx) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+ if (reg_num & 1) {
+ gen_exception_illegal(ctx);
+ return NULL;
+ } else {
+#ifdef TARGET_RISCV32
+ TCGv_i64 t = ftemp_new(ctx);
+ if (reg_num == 0) {
+ tcg_gen_concat_i32_i64(t, ctx->zero, ctx->zero);
+ } else {
+ tcg_gen_concat_i32_i64(t, cpu_gpr[reg_num],
cpu_gpr[reg_num + 1]);
+ }
+ return t;
+ }
+#else
+ if (reg_num == 0) {
+ return ctx->zero;
+ } else {
+ TCGv_i64 t = ftemp_new(ctx);
+ tcg_gen_deposit_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num +
1], 32, 32);
+ return t;
+ }
+ }
+ case MXL_RV64:
+ if (reg_num == 0) {
+ return ctx->zero;
+ } else {
+ return cpu_gpr[reg_num];
+ }
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ return cpu_fpr[reg_num];
+ }
+}
+
+static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
+{
+ if (ctx->ext_zfinx) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+ return ftemp_new(ctx);
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ if (reg_num == 0) {
+ return ftemp_new(ctx);
+ } else {
+ return cpu_gpr[reg_num];
+ }
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ return cpu_fpr[reg_num];
+ }
+}
+
+static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
+{
+ if (ctx->ext_zfinx) {
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+#ifdef TARGET_RISCV32
+ tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
+ break;
+#else
+ tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
+ break;
+ case MXL_RV64:
+ tcg_gen_mov_i64(cpu_gpr[reg_num], t);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ }
+ } else {
+ tcg_gen_mov_i64(cpu_fpr[reg_num], t);
+ }
+}
+
+static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
+{
+ if (ctx->ext_zfinx) {
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+ if (reg_num & 1) {
+ gen_exception_illegal(ctx);
+ } else {
+#ifdef TARGET_RISCV32
+ tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
+ tcg_gen_extrh_i64_i32(cpu_gpr[reg_num + 1], t);
+ }
+ break;
+#else
+ tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
+ tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32);
+ }
+ break;
+ case MXL_RV64:
+ tcg_gen_mov_i64(cpu_gpr[reg_num], t);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ }
+ } else {
+ tcg_gen_mov_i64(cpu_fpr[reg_num], t);
+ }
+}
+
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
@@ -727,6 +889,8 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->cs = cs;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
+ ctx->nftemp = 0;
+ memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
ctx->pm_mask = pm_mask[priv];
@@ -761,6 +925,11 @@ static void riscv_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
ctx->temp[i] = NULL;
}
ctx->ntemp = 0;
+ for (int i = ctx->nftemp - 1; i >= 0; --i) {
+ tcg_temp_free_i64(ctx->ftemp[i]);
+ ctx->ftemp[i] = NULL;
+ }
+ ctx->nftemp = 0;
if (ctx->base.is_jmp == DISAS_NEXT) {
target_ulong page_start;
--
2.17.1
- [PATCH 0/6] support subsets of Float-Point in Integer Registers extensions, liweiwei, 2021/12/23
- [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}, liweiwei, 2021/12/23
- [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties, liweiwei, 2021/12/23
- [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin, liweiwei, 2021/12/23
- [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx,
liweiwei <=
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, Richard Henderson, 2021/12/24
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/24
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, Richard Henderson, 2021/12/25
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/25
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/25
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, Richard Henderson, 2021/12/25
[PATCH 3/6] target/riscv: add support for zfinx, liweiwei, 2021/12/23
[PATCH 4/6] target/riscv: add support for zdinx, liweiwei, 2021/12/23