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[PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instruct
From: |
frank . chang |
Subject: |
[PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions |
Date: |
Fri, 10 Dec 2021 15:56:45 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aed230e1ad..cc95b69255 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3387,28 +3387,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
/* Vector Floating-Point MIN/MAX Instructions */
-RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
-RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
-RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
+RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
+RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
+RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
-RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
-RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
+RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
+RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
+RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
GEN_VEXT_VF(vfmin_vf_h, 2, 2)
GEN_VEXT_VF(vfmin_vf_w, 4, 4)
GEN_VEXT_VF(vfmin_vf_d, 8, 8)
-RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
+RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
+RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
+RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
+RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
+RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
+RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
GEN_VEXT_VF(vfmax_vf_h, 2, 2)
GEN_VEXT_VF(vfmax_vf_w, 4, 4)
GEN_VEXT_VF(vfmax_vf_d, 8, 8)
--
2.31.1
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, (continued)
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/12/10
- [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/12/10
- [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/12/10
- [PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/12/10
- [PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/12/10
- [PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/12/10
- [PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/12/10
- [PATCH v11 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/12/10
- [PATCH v11 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/12/10
- [PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/12/10
- [PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions,
frank . chang <=
- [PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/12/10
- [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/12/10
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/12/10
- [PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/12/10
- [PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/12/10
- [PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/12/10
- [PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/12/10