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[PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN |
Date: |
Thu, 11 Nov 2021 13:57:54 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 8 +++++---
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c5098380dd..a67965efe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
#endif
/* Vector functions */
-DEF_HELPER_3(vsetvl, tl, env, tl, tl)
+DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl)
DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 17ee3babef..f5aabd5263 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx)));
gen_set_gpr(ctx, a->rd, dst);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
@@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx)));
gen_set_gpr(ctx, a->rd, dst);
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index b02ccefa4d..1a7ee46d46 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -27,14 +27,16 @@
#include <math.h>
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
- target_ulong s2)
+ target_ulong s2, target_ulong xlen)
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
- bool vill = FIELD_EX64(s2, VTYPE, VILL);
- target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+ bool vill = (s2 >> (xlen - 1)) & 0x1;
+ target_ulong reserved = s2 &
+ MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
--
2.25.1
- Re: [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], (continued)
- [PATCH v3 10/20] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/11
- [PATCH v3 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/11
- [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN,
LIU Zhiwei <=
- [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
- [PATCH v3 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
- [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11