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[PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug o
From: |
frank . chang |
Subject: |
[PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns |
Date: |
Fri, 29 Oct 2021 16:58:27 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index df45c1620c1..3da4f3b1e62 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -374,10 +374,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.25.1
- [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, (continued)
- [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/10/29
- [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/10/29
- [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/10/29
- [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/10/29
- [PATCH v9 15/76] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/10/29
- [PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/10/29
- [PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2021/10/29
- [PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 2021/10/29
- [PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/10/29
- [PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/10/29
- [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns,
frank . chang <=
- [PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/10/29
- [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/10/29
- [PATCH v9 21/76] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/10/29
- [PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/10/29
- [PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2021/10/29
- [PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/10/29
- [PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/10/29
- [PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/10/29
- [PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/10/29
- [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/10/29