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Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and Machin
From: |
Igor Mammedov |
Subject: |
Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id |
Date: |
Thu, 21 Oct 2021 10:44:21 +0200 |
On Wed, 20 Oct 2021 09:41:08 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/opentitan.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 9803ae6d70..5d568ea58a 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -19,6 +19,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "hw/riscv/opentitan.h"
> #include "qapi/error.h"
> #include "hw/boards.h"
> @@ -64,20 +65,25 @@ static const MemMapEntry ibex_memmap[] = {
>
> static void opentitan_board_init(MachineState *machine)
> {
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> +
> + if (machine->ram_size != mc->default_ram_size) {
> + char *sz = size_to_str(mc->default_ram_size);
> + error_report("Invalid RAM size, should be %s", sz);
> + g_free(sz);
> + exit(EXIT_FAILURE);
> + }
>
> /* Initialize SoC */
> object_initialize_child(OBJECT(machine), "soc", &s->soc,
> TYPE_RISCV_IBEX_SOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> - memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
> - memmap[IBEX_DEV_RAM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[IBEX_DEV_RAM].base, main_mem);
> + memmap[IBEX_DEV_RAM].base, machine->ram);
>
> if (machine->firmware) {
> riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base,
> NULL);
> @@ -95,6 +101,8 @@ static void opentitan_machine_init(MachineClass *mc)
> mc->init = opentitan_board_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> + mc->default_ram_id = "riscv.lowrisc.ibex.ram";
> + mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> DEFINE_MACHINE("opentitan", opentitan_machine_init)
- [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines, Bin Meng, 2021/10/19
- [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/19
- [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/19
- [PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/19
- [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/19
- [PATCH v2 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/19
- [PATCH v2 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/19