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[PATCH v15 0/8] RISC-V Pointer Masking implementation
From: |
Alexey Baturo |
Subject: |
[PATCH v15 0/8] RISC-V Pointer Masking implementation |
Date: |
Wed, 20 Oct 2021 13:19:27 +0300 |
v14:
Addressed Richard's comments from previous series.
v13:
Rebased QEMU and addressed Richard's comment.
v12:
Updated function for adjusting address with pointer masking to allocate and use
temp register.
v11:
Addressed a few style issues Alistair mentioned in the previous review.
If this patch series would be accepted, I think my further attention would be
to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned
previously
Thanks!
Alexey Baturo (7):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Add CSR defines for RISC-V PM extension
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
the h-mode
[RISCV_PM] Add J extension state description
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
[RISCV_PM] Allow experimental J-ext to be turned on
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 31 +++
target/riscv/cpu.h | 33 +++
target/riscv/cpu_bits.h | 96 ++++++++
target/riscv/csr.c | 285 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/machine.c | 27 +++
target/riscv/translate.c | 43 ++++
10 files changed, 524 insertions(+)
--
2.30.2
- [PATCH v15 0/8] RISC-V Pointer Masking implementation,
Alexey Baturo <=
- [PATCH v15 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/10/20
- [PATCH v15 8/8] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2021/10/20
- [PATCH v15 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension, Alexey Baturo, 2021/10/20
- [PATCH v15 1/8] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2021/10/20
- [PATCH v15 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2021/10/20
- [PATCH v15 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/10/20
- [PATCH v15 4/8] [RISCV_PM] Add J extension state description, Alexey Baturo, 2021/10/20
- [PATCH v15 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2021/10/20
- Re: [PATCH v15 0/8] RISC-V Pointer Masking implementation, Alistair Francis, 2021/10/21