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[PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructio
From: |
frank . chang |
Subject: |
[PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions |
Date: |
Fri, 15 Oct 2021 15:45:57 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c | 4 ----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 2fe8f4a3c2f..e59fc5a01d8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2651,7 +2651,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 71d7b1e8796..f883fdf4749 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4231,7 +4231,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4241,9 +4240,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
#define DO_NAND(N, M) (!(N & M))
--
2.25.1
- Re: [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions, (continued)
- [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/10/15
- [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/10/15
- [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/10/15
- [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/10/15
- [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/10/15
- [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/10/15
- [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/10/15
- [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/10/15
- [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions,
frank . chang <=
- [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/10/15
- [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/10/15
- [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/10/15
- [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/10/15
- [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/10/15
- [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/10/15
- [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/10/15
- [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/10/15
- [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/10/15