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Re: [PATCH v4 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only |
Date: |
Thu, 7 Oct 2021 07:36:56 +1000 |
On Thu, Oct 7, 2021 at 4:12 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for riscv linux-user.
>
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Cc: qemu-riscv@nongnu.org
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> linux-user/riscv/cpu_loop.c | 7 -------
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 21 +--------------------
> 3 files changed, 2 insertions(+), 28 deletions(-)
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 9859a366e4..aef019b1c8 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env)
> sigcode = TARGET_TRAP_BRKPT;
> sigaddr = env->pc;
> break;
> - case RISCV_EXCP_INST_PAGE_FAULT:
> - case RISCV_EXCP_LOAD_PAGE_FAULT:
> - case RISCV_EXCP_STORE_PAGE_FAULT:
> - signum = TARGET_SIGSEGV;
> - sigcode = TARGET_SEGV_MAPERR;
> - sigaddr = env->badaddr;
> - break;
> case RISCV_EXCP_SEMIHOST:
> env->gpr[xA0] = do_common_semihosting(cs);
> env->pc += 4;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7c626d89cd..0292a72feb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -675,9 +675,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> static const struct TCGCPUOps riscv_tcg_ops = {
> .initialize = riscv_translate_init,
> .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> - .tlb_fill = riscv_cpu_tlb_fill,
>
> #ifndef CONFIG_USER_ONLY
> + .tlb_fill = riscv_cpu_tlb_fill,
> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> .do_interrupt = riscv_cpu_do_interrupt,
> .do_transaction_failed = riscv_cpu_do_transaction_failed,
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d41d5cd27c..b520d6fc78 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
> addr,
> riscv_cpu_two_stage_lookup(mmu_idx);
> riscv_raise_exception(env, cs->exception_index, retaddr);
> }
> -#endif /* !CONFIG_USER_ONLY */
>
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> -#ifndef CONFIG_USER_ONLY
> vaddr im_address;
> hwaddr pa = 0;
> int prot, prot2, prot_pmp;
> @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
> }
>
> return true;
> -
> -#else
> - switch (access_type) {
> - case MMU_INST_FETCH:
> - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
> - break;
> - case MMU_DATA_LOAD:
> - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
> - break;
> - case MMU_DATA_STORE:
> - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - env->badaddr = address;
> - cpu_loop_exit_restore(cs, retaddr);
> -#endif
> }
> +#endif /* !CONFIG_USER_ONLY */
>
> /*
> * Handle Traps
> --
> 2.25.1
>
>