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[PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit
From: |
Frédéric Pétrot |
Subject: |
[PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns |
Date: |
Wed, 6 Oct 2021 23:28:29 +0200 |
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We have a slight issue with returning 128-bit values: we use the globals
we added to support div/rem insns to that end.
Theses helpers all call a unique function that is currently a stub.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 4 ++++
target/riscv/helper.h | 3 +++
target/riscv/csr.c | 7 +++++++
target/riscv/op_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a2d7d65efb..911fdc4ecf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -506,6 +506,10 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState
*env, int csrno,
target_ulong new_value,
target_ulong write_mask);
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask);
+
typedef struct {
const char *name;
riscv_csr_predicate_fn predicate;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 01d885d566..d1176649f1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,6 +68,9 @@ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
+DEF_HELPER_2(csrr_i128, void, env, int)
+DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
+DEF_HELPER_6(csrrw_i128, void, env, int, tl, tl, tl, tl)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_2(sret, tl, env, tl)
DEF_HELPER_2(mret, tl, env, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd3216..9529119238 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1492,6 +1492,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask)
+{
+ return RISCV_EXCP_ILLEGAL_INST;
+}
+
/*
* Debugger support. If not in user mode, set env->debugger before the
* riscv_csrrw call and clear it after the call.
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..753eb35000 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -69,6 +69,50 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
return val;
}
+void helper_csrr_i128(CPURISCVState *env, int csr)
+{
+ Int128 rv = int128_zero();
+ RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+ int128_zero(),
+ int128_zero());
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ env->hlpr[0] = int128_getlo(rv);
+ env->hlpr[1] = int128_gethi(rv);
+}
+
+void helper_csrw_i128(CPURISCVState *env, int csr,
+ target_ulong srcl, target_ulong srch)
+{
+ RISCVException ret = riscv_csrrw_i128(env, csr, NULL,
+ int128_make128(srcl, srch),
+ UINT128_MAX);
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+}
+
+void helper_csrrw_i128(CPURISCVState *env, int csr,
+ target_ulong srcl, target_ulong srch,
+ target_ulong maskl, target_ulong maskh)
+{
+ Int128 rv = int128_zero();
+ RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+ int128_make128(srcl, srch),
+ int128_make128(maskl, maskh));
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ env->hlpr[0] = int128_getlo(rv);
+ env->hlpr[1] = int128_gethi(rv);
+}
+
#ifndef CONFIG_USER_ONLY
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
--
2.33.0
- [PATCH v2 12/27] target/riscv: moving some insns close to similar insns, (continued)
- [PATCH v2 12/27] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 16/27] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/06
- [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 13/27] target/riscv: rename a few gen function helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic, Frédéric Pétrot, 2021/10/06
- [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit, Frédéric Pétrot, 2021/10/06
- [PATCH v2 22/27] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/06
- [PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns,
Frédéric Pétrot <=
- [PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/06
- [PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs, Frédéric Pétrot, 2021/10/06
- [PATCH v2 27/27] target/riscv: support for 128-bit satp, Frédéric Pétrot, 2021/10/06
- [PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem, Frédéric Pétrot, 2021/10/06
- Re: [PATCH v2 00/27] Adding partial support for 128-bit riscv target, Philippe Mathieu-Daudé, 2021/10/07