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[PATCH v10 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs
From: |
Alexey Baturo |
Subject: |
[PATCH v10 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs |
Date: |
Sun, 29 Aug 2021 20:51:17 +0300 |
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4178eecbec..ab8c81cb5e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -300,6 +300,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
+ if (riscv_has_ext(env, RVJ)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ switch (env->priv) {
+ case PRV_U:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+ env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+ env->upmmask);
+ break;
+ case PRV_S:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+ env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+ env->spmmask);
+ break;
+ case PRV_M:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+ env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+ env->mpmmask);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
- [PATCH v10 0/7] RISC-V Pointer Masking implementation, Alexey Baturo, 2021/08/29
- [PATCH v10 1/7] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2021/08/29
- [PATCH v10 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension, Alexey Baturo, 2021/08/29
- [PATCH v10 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/08/29
- [PATCH v10 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs,
Alexey Baturo <=
- [PATCH v10 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/08/29
- [PATCH v10 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2021/08/29
- [PATCH v10 7/7] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2021/08/29