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Re: [PATCH v5 05/17] target/riscv: rvb: pack two words into one register
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 05/17] target/riscv: rvb: pack two words into one register |
Date: |
Tue, 27 Apr 2021 16:05:37 +1000 |
On Wed, Apr 21, 2021 at 2:17 PM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32-64.decode | 3 ++
> target/riscv/insn32.decode | 3 ++
> target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++++++++++++++++
> target/riscv/translate.c | 40 +++++++++++++++++++++++++
> 4 files changed, 76 insertions(+)
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 89498a9a28a..d28c0bcf2c1 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -91,3 +91,6 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
> +
> +packw 0000100 .......... 100 ..... 0111011 @r
> +packuw 0100100 .......... 100 ..... 0111011 @r
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index d0b3f109b4e..7f32b8c6d15 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -602,3 +602,6 @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2
> andn 0100000 .......... 111 ..... 0110011 @r
> orn 0100000 .......... 110 ..... 0110011 @r
> xnor 0100000 .......... 100 ..... 0110011 @r
> +pack 0000100 .......... 100 ..... 0110011 @r
> +packu 0100100 .......... 100 ..... 0110011 @r
> +packh 0000100 .......... 111 ..... 0110011 @r
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 73c4693a263..2d24dafac09 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
> return gen_arith(ctx, a, tcg_gen_eqv_tl);
> }
>
> +static bool trans_pack(DisasContext *ctx, arg_pack *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, gen_pack);
> +}
> +
> +static bool trans_packu(DisasContext *ctx, arg_packu *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, gen_packu);
> +}
> +
> +static bool trans_packh(DisasContext *ctx, arg_packh *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, gen_packh);
> +}
> +
> /* RV64-only instructions */
> #ifdef TARGET_RISCV64
>
> @@ -74,4 +92,16 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> return gen_unary(ctx, a, gen_cpopw);
> }
>
> +static bool trans_packw(DisasContext *ctx, arg_packw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, gen_packw);
> +}
> +
> +static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, gen_packuw);
> +}
> +
> #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b20a58c63b4..4333207aeff 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -536,6 +536,29 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
>
> #endif
>
> +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_deposit_tl(ret, arg1, arg2,
> + TARGET_LONG_BITS / 2,
> + TARGET_LONG_BITS / 2);
> +}
> +
> +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
> + tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext8u_tl(t, arg2);
> + tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
> + tcg_temp_free(t);
> +}
> +
> #ifdef TARGET_RISCV64
>
> static void gen_ctzw(TCGv ret, TCGv arg1)
> @@ -557,6 +580,23 @@ static void gen_cpopw(TCGv ret, TCGv arg1)
> tcg_gen_ctpop_tl(ret, arg1);
> }
>
> +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext16s_i64(t, arg2);
> + tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_shri_i64(t, arg1, 16);
> + tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
> + tcg_gen_ext32s_i64(ret, ret);
> + tcg_temp_free(t);
> +}
> +
> #endif
>
> static bool gen_arith(DisasContext *ctx, arg_r *a,
> --
> 2.17.1
>
>
- [PATCH v5 00/17] support subsets of bitmanip extension, frank . chang, 2021/04/21
- [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2021/04/21
- [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2021/04/21
- [PATCH v5 03/17] target/riscv: rvb: count bits set, frank . chang, 2021/04/21
- [PATCH v5 04/17] target/riscv: rvb: logic-with-negate, frank . chang, 2021/04/21
- [PATCH v5 05/17] target/riscv: rvb: pack two words into one register, frank . chang, 2021/04/21
- Re: [PATCH v5 05/17] target/riscv: rvb: pack two words into one register,
Alistair Francis <=
- [PATCH v5 06/17] target/riscv: rvb: min/max instructions, frank . chang, 2021/04/21
- [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions, frank . chang, 2021/04/21
- [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, frank . chang, 2021/04/21
- [PATCH v5 09/17] target/riscv: rvb: single-bit instructions, frank . chang, 2021/04/21
- [PATCH v5 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/04/21
- [PATCH v5 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/04/21
- [PATCH v5 12/17] target/riscv: rvb: generalized reverse, frank . chang, 2021/04/21
- [PATCH v5 13/17] target/riscv: rvb: generalized or-combine, frank . chang, 2021/04/21