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Re:
From: |
Alistair Francis |
Subject: |
Re: |
Date: |
Thu, 15 Apr 2021 22:27:26 +0000 |
User-agent: |
Evolution 3.38.4 |
On Thu, 2021-04-15 at 15:41 +0200, Emmanuel Blot wrote:
> Date: Tue, 13 Apr 2021 18:01:52 +0200
> Subject: [PATCH] target/riscv: fix exception index on instruction
> access fault
>
> When no MMU is used and the guest code attempts to fetch an instruction
> from an invalid memory location, the exception index defaults to a data
> load access fault, rather an instruction access fault.
>
> Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Thanks for the patch. Can you send the patch to the QEMU mailling list?
qemu-devel@nongnu.org
Alistair
>
> ---
> target/riscv/cpu_helper.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 21c54ef5613..4e107b1bd23 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -691,8 +691,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs,
> hwaddr physaddr,
>
> if (access_type == MMU_DATA_STORE) {
> cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> - } else {
> + } else if (access_type == MMU_DATA_LOAD) {
> cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
> + } else {
> + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
> }
>
> env->badaddr = addr;
- [no subject], Emmanuel Blot, 2021/04/15
- Re:, Palmer Dabbelt, 2021/04/15
- Re:,
Alistair Francis <=