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[RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans
From: |
frank . chang |
Subject: |
[RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans |
Date: |
Thu, 6 Aug 2020 18:46:15 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 525aff06815..8a6050f6b32 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2156,6 +2156,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2,
{
TCGv_ptr dest, src2, mask;
TCGv_i32 desc;
+ TCGv_i64 t1;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2169,12 +2170,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2,
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
+ /* NaN-box f[rs1] */
+ t1 = tcg_temp_new_i64();
+ do_nanbox(s, t1, cpu_fpr[rs1]);
+
+ fn(dest, mask, t1, src2, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(t1);
mark_vs_dirty(s);
gen_set_label(over);
return true;
--
2.17.1
- Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, (continued)
- [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/06
- [RFC v3 14/71] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/08/06
- [RFC v3 16/71] target/riscv: add fp16 nan-box check generator function, frank . chang, 2020/08/06
- [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/08/06
- [RFC v3 17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/08/06
- [RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans,
frank . chang <=
- [RFC v3 19/71] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/08/06
- [RFC v3 20/71] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/08/06
- [RFC v3 21/71] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/08/06
- [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/08/06
- [RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/08/06
- [RFC v3 24/71] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/06
- [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/06
- [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/06